Capacity on demand using signaling bus control

• US 20060136680A1
• Filed: 12/17/2004
• Published: 06/22/2006
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Carter, Benjamin F. III, Levesque, Stephen Roland, Borkenhagen, John Michael
• Granted Patent: US 7,392,418 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 9/5061 Partitioning or combining of resources

Abstract

An apparatus and method is disclosed for providing capacity on demand using control to alter latency and/or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity in the computing system. Alternatively, upon authorization, latency of data transmissions over the signaling bus is reduced. In another alternative, upon authorization, memory timings are adjusted to speed up memory fetches and stores.

Claims

1. A computing system having a controllable capacity, comprising:

a processor; and

a signaling bus coupled to the processor;

wherein the controllable capacity of the computing system is controlled by monitoring demand on the computing system and altering the controllable capacity responsive to demand by controlling a characteristic of the signaling bus.

2. The computing system of claim 1, wherein the characteristic of the signaling bus is bandwidth.

3. The computing system of claim 2, further comprising a means for dynamically changing a percentage of dead cycles on the signaling bus.

4. The computing system of claim 3, the means for dynamically changing the percentage of dead cycles on the signaling bus comprises:

a bus ready signal coupled to the processor capable of indicating that data transmitting on the signaling bus should not be used; and

a capacity on demand register capable of storing a currently authorized capacity of the computing system, the capacity on demand register coupled to the bus ready signal.

5. The computing system of claim 4, further comprising:

a shift register coupled to the capacity on demand register and to the bus ready signal, the shift register capable of being initialized by the capacity on demand register, the shift register further configured to rotate one bit position per cycle of the signaling bus.

6. The computing system of claim 1, wherein the characteristic of the signaling bus is latency.

7. The computing system of claim 6, further comprising means for dynamically delaying transmission of data over the signaling bus.

8. The computing system of claim 7, the means for dynamically delaying transmission of data over the signaling bus comprising:

a capacity on demand register capable of holding a currently authorized capacity for the computing system; and

a memory data delay, coupled to the capacity on demand register, capable of delaying transmission of data on the signaling bus responsive to the currently authorized capacity for the computing system.

9. The computing system of claim 7, the means for dynamically delaying transmission of data over the signaling bus comprising:

a capacity on demand register capable of holding a currently authorized capacity for the computing system;

a memory capable of storing data required by the processor; and

a memory sequencer coupled to the memory and to the signaling bus, the memory sequencer capable of controlling the memory using timing values responsive to the currently authorized capacity for the computing system.

10. The computing system of claim 7, the means for dynamically delaying transmission of data over the signaling bus comprising:

a capacity on demand register capable of holding a currently authorized capacity for the computing system; and

a snoop mechanism coupled to the signaling bus and to the capacity on demand register, the snoop mechanism capable of inserting snoop stalls responsive to the currently authorized capacity for the computing system.

11. A method of providing capacity on demand for a computer system comprising the steps of:

monitoring an indicator that relates capacity and demand;

if capacity and demand differ by a predetermined amount, requesting a change in capacity from an authorizing source;

receiving approval from the authorizing source for a change in capacity; and

upon approval by the authorizing source, changing the capacity of the computing system by changing a bandwidth or a latency of a signaling bus.

12. The method of claim 11, wherein the indicator is one or more elements selected from the group consisting of:

a measurement of response time;

a measurement of transactions per interval of time;

a measurement of throughput;

a measurement of signaling bus utilization; and

a measurement of floating point operations during an interval of time.

13. The method of claim 11, the step of requesting a change in capacity from an authorizing source further comprising the step encrypting the request for a change in capacity.

14. The method of claim 13, the step of encrypting the request for a change in capacity further including the step of including an identifier that uniquely identifies the computing system.

15. The method of claim 11, the step of receiving approval for a change in capacity further including the steps of:

receiving an encrypted message from the authorizing source; and

decrypting the encrypted message.

16. The method of claim 15, further comprising the step of storing a currently authorized capacity in a capacity on demand (COD) register.

17. The method of claim 11, the step of changing the capacity of the computing system by changing the bandwidth or the latency of a signaling bus including the step of changing a percentage of dead cycles on the signaling bus.

18. The method of claim 11, the step of changing the capacity of the computing system by changing the bandwidth or the latency of a signaling bus including the step of changing a wait time before data is transmitted on the signaling bus.

19. The method of claim 11, the step of changing the capacity of the computing system by changing the bandwidth or the latency of a signaling bus including the step of changing a memory timing.

20. The method of claim 11, the step of changing the capacity of the computing system by changing the bandwidth or the latency of a signaling bus including the step of changing a snoop stall.

21. A program product that, when executed on a suitable processor, executes the steps of claim 11.

22. A method for deploying capacity on demand within a computing system comprising integrating computer readable code into a computing system, wherein the code in combination with the computing system is capable of performing the following:

monitoring an indicator that relates capacity and demand;

if capacity and demand differ by a predetermined amount, requesting a change in capacity from an authorizing source;

receiving approval from the authorizing source for a change in capacity; and

upon approval by the authorizing source, changing the capacity of the computing system by changing a bandwidth or a latency of a signaling bus.