Unit-based layout system for passive IC devices

• US 20060136856A1
• Filed: 01/19/2005
• Published: 06/22/2006
• Est. Priority Date: 12/17/2004
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: SpringSoft, Inc. (Synopsys Incorporated)
• Inventors: Tang, Shyh-An, Hsu, Ya-Chin
• Granted Patent: US 7,257,794 B2
• Time in Patent Office: Days
• US Class Current: 716/122
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A computer-aided design tool generates a layout for a passive device, such as a resistor or a capacitor, to be incorporated into an integrated circuit. The layout is based on a model describing the passive device as being formed by a variable number of interconnected instances of a device unit, such as a resistor segment or a capacitor block. User-supplied Input parameter values control the number of instances of the device unit included in the passive device layout, the relative positions of the device unit instances, and characteristics of their internal layouts. The tool also generates a display of a representation of the passive device layout and provides a graphical interface enabling the user to modify various aspects of the passive device layout by altering its displayed representation.

Claims

1. Computer-readable media containing program instructions which, when read and executed by a computer, causes the computer to carry out a method for generating layouts for passive devices to be formed within an integrated circuit (IC), wherein the method comprises, for each passive device, the steps of:

a. receiving as input a layout model of the passive device including a description of the passive device layout as being formed by a variable number of instances of a device unit, wherein the number and relative positions of the device unit instances forming the passive device and characteristics of an internal layout of each device unit instance are variable functions of input parameter values;

b. receiving the parameter values as input;

c. generating a layout for the passive device in accordance with the description included in the layout model, wherein the number of instances of the device unit form the passive devices, their relative positions and the characteristics of the internal layout of each device unit instance are controlled in accordance with the variable functions included in the layout model and the received parameter values; and

d. displaying a graphical representation of the passive device layout generated at step c.

2. The computer-readable media in accordance with claim 1 wherein the method further comprises the steps of

e. providing a graphical user interface enabling a user to alter the displayed graphical representation of the passive device layout;

and

f. altering the passive device layout when the user alters its displayed graphical representation to render the passive device layout consistent with its graphical representation.

3. The computer-readable media in accordance with claim 1 wherein parameter values received at step b select spacing between the device unit instances within the passive device layout.

4. The computer-readable media in accordance with claim 1 wherein one portion of the parameter values received at step b are functions of IC semiconductor technology design rules.

5. The computer-readable media in accordance with claim 4 wherein a user supplies another portion of the parameter values received at step b.

6. The computer-readable media in accordance with claim 1 wherein the internal layout of each device unit instance included in the passive device layout generated at step c includes a plurality of objects, and wherein the variable functions and received parameter values control at least one dimension of at least one of the objects.

7. The computer-readable media in accordance with claim 1 wherein the internal layout of each device unit instance included in the passive device layout generated at step c includes a plurality of objects, and wherein the variable functions and received parameter values control spacing between at least two of the objects.

8. The computer-readable media in accordance with claim 1 wherein one portion of the received parameter values are functions of IC semiconductor technology design rules specifying minimum spacing between structures within a semiconductor, and that portion of the received parameter values influences spacing between objects forming the device unit instances.

9. The computer-readable media in accordance with claim 8 wherein a user supplies another portion of the received parameter values that influence the number of device unit instances included in the passive device.

10. The computer-readable media in accordance with claim 9 wherein said another portion of the received parameter values also influence characteristics of the internal layouts of the device unit instances.

11. The computer-readable media in accordance with claim 1

wherein each passive device is a resistor such that each passive device layout is a resistor layout,

wherein each device unit instance forming the resistor is a resistor segment comprising:

a body formed by resistive material within the IC, and

a plurality of conductive contact structures connected to the body, and

wherein conductors interconnect contact structures of the device unit instances.

12. The computer-readable media in accordance with claim 11 wherein a dimension of the body of each resistor segment is independently controlled by the received parameter values.

13. The computer-readable media in accordance with claim 11 wherein a number of conductive contact structures connected to the body of each resistor segment is a variable function of at least one of the received parameter values.

14. The computer-readable media in accordance with claim 11

wherein the received parameter values specify a resistance of each resistor segment,

wherein the resistance of each resistor segment is a function of a dimension of the body of the resistor segment, and

wherein that dimension of the body of each resistor segment is selected at step c so that the resistor segment has the resistance specified by the received parameter values.

15. The computer-readable media in accordance with claim 11 wherein the method further comprises the steps of

e. providing a graphical interface enabling a user to alter the displayed graphical representation of each resistor layout;

and

f. altering each resistor layout when the user alters its displayed graphical representation, so that the resistor layout is consistent with its graphical representation.

16. The computer-readable media in accordance with claim 15, wherein the graphical interface enables the user to alter the displayed graphical representation of a displayed resistor layout by altering a position of a resistor segment instance within that resistor layout.

17. The computer-readable media in accordance with claim 15, wherein the graphical interface enables the user to alter the displayed graphical representation of the displayed resistor layout by splitting the resistor layout representation into two separate new resistor layout representations, each including a separate subset of its resistor segment instances, wherein the resistor layout is altered at step f by replacing it with two resistor layouts, each consistent with a separate one of the two resistor new layout representations.

18. The computer-readable media in accordance with claim 15, wherein the graphical interface enables the user to alter the displayed graphical representation of the displayed resistor layout formed by a plurality of resistor segments, by replacing representations of at least two of the resistor segments with a representation of a single resistor segment having a resistance equal to a sum of resistances of the plurality of resistor segments.

19. The computer-readable media in accordance with claim 15, wherein the graphical interface enables the user to alter the displayed graphical representation of the resistor layout by replacing a representation of a single resistor segment of the resistor layout with representations of a plurality of resistor segments, wherein the single resistor segment has a resistance equal to a sum of resistances of the plurality of resistor segments.

20. The computer-readable media in accordance with claim 15, wherein the graphical interface enables the user to replace concurrently displayed representations of layouts of a plurality of resistors with a representation of a layout of a single resistor having a resistance equal to a sum of resistances of the plurality of resistors.

21. The computer-readable media in accordance with claim 15 wherein the graphical interface enables the user to independently alter characteristics of the internal layout of any individual resistor segment by altering parameter values controlling those characteristics.

22. The computer-readable media in accordance with claim 15 wherein the graphical interface enables the user to select representations of two resistor segments forming a resistor and specify that their positions will be swapped.

23. The computer-readable media in accordance with claim 15 wherein the graphical interface enables the user to alter a manner in which segments are interconnected.

24. The computer-readable media in accordance with claim 1

wherein each passive device is a capacitor such that each passive device layout is a capacitor layout,

wherein the layout model describes the device unit as a capacitor block comprising:

a first conductive plate formed within the IC, and

a first conductive contact structure formed within the IC and connected to the plate, wherein conductors interconnect the first conductive contract structures of all instances of the capacitor block forming the capacitor.

25. The computer-readable media in accordance with claim 24

wherein the device model also describes the capacitor block as optionally comprising:

a second conductive plate formed within the IC, and

a second conductive contact structure, wherein conductors interconnect the second contact structures of all instances of the capacitor block forming the capacitor.

26. The computer-readable media in accordance with claim 25 wherein the received parameter values control whether instances of the capacitor blocks forming a capacitor include the second conductive plate and the second conductive contract structure.

27. The computer-readable media in accordance with claim 24 wherein the received parameter values control whether the first conductive plates of all capacitor block instances forming a capacitor contact one another or are spaced apart

28. The computer-readable media in accordance with claim 24 wherein the received parameters control a dimension of the first conductive plate of each capacitor block instance.

29. The computer-readable media in accordance with claim 24

wherein the received parameter values specify a capacitance of the capacitor block,

wherein the capacitance of the capacitor block is a function of a dimension of the first conductive plate, and

wherein that dimension of the first conductive plate is selected at step c so that each instance of the capacitor block forming capacitor has the capacitance specified by the received parameter values.

30. The computer-readable media in accordance with claim 24 wherein the received parameter values control a shape of the capacitor block.

31. The computer-readable media in accordance with claim 24 wherein the method further comprises the steps of

e. providing a graphical interface enabling a user to alter the displayed graphical representation of each capacitor layout;

and

f. altering each capacitor layout when the user alters its displayed graphical representation, so that capacitor layout is consistent with its graphical representation.

32. The computer-readable media in accordance with claim 31, wherein the graphical interface enables the user to alter the displayed graphical representation of any displayed capacitor layout at by altering a position of a capacitor block instance within that capacitor layout.

33. The computer-readable media in accordance with claim 31, wherein the graphical interface enables the user to alter the displayed graphical representation of any capacitor layout at by splitting the capacitor layout representation into two new separate capacitor layout representations, each including a separate subset of its capacitor block instances, wherein the capacitor layout is altered at step f by replacing it with two capacitor layouts, each consistent with a separate one of the two new capacitor layout representations.

34. The computer-readable media in accordance with claim 31, wherein the graphical interface enables the user to alter a shape of each capacitor block instance.

35. The computer-readable media in accordance with claim 31, wherein the graphical interface enables the user to replace concurrently displayed representations of layouts of a plurality of capacitors with a representation of a layout of a single capacitor having a capacitance equal to a sum of capacitances of the plurality of capacitors.