Novel combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications

• US 20060138245A1
• Filed: 12/16/2005
• Published: 06/29/2006
• Est. Priority Date: 12/28/2004
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter W.
• Granted Patent: US 7,369,438 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that each array may be addressed with common addressing signals. The combination volatile and nonvolatile memory integrated circuit further has a memory control circuit in communication with external circuitry to receive address, command, and data signals. The memory control circuit interprets the address, command, and data signals, and for transfer to the volatile memory array and the nonvolatile memory arrays for reading, writing, programming, and erasing the volatile and nonvolatile memory arrays. The volatile memory array is may be a SRAM, a pseudo SRAM, or a DRAM. Any of the nonvolatile memory arrays maybe masked programmed ROM arrays, NAND configured flash memory NAND configured EEPROM.

Claims

1. A combination volatile and nonvolatile memory integrated circuit placed on a substrate comprising

at least one volatile memory array placed on said substrate;

a plurality of nonvolatile memory arrays placed on said substrate and having an address associated with said volatile memory array; and

a memory control circuit in communication with external circuitry to receive address, command, and data signals, to interpret said address, command, and data signals, and in communication with said volatile memory array and said plurality of nonvolatile memory arrays to transfer said address, command and data signals for reading, writing, programming, and erasing said volatile and nonvolatile memory arrays.

2. The combination volatile and nonvolatile memory integrated circuit of claim 1 further comprising:

a voltage generator that generates a very large positive programming voltage and a very large negative erasing voltage and is in communication with said nonvolatile memory arrays to transfer said very large positive programming voltage to selected first sub-arrays of said nonvolatile memory arrays for programming said selected first sub-arrays and to transfer said very large negative erasing voltage to selected second sub-arrays of said nonvolatile memory arrays for erasing said selected second sub-arrays.

3. The combination volatile and nonvolatile memory integrated circuit of claim 1 wherein said volatile memory array is selected from a set of volatile random access memories consisting of a static random access memory, a pseudo static random access memory, and a dynamic random access memory.

4. The combination volatile and nonvolatile memory integrated circuit of claim 1 wherein any of the plurality of the nonvolatile memory arrays is masked programmed read only memory arrays for retention of permanent unchangeable data.

5. The combination volatile and nonvolatile memory integrated circuit of claim 1 wherein any of the plurality of the nonvolatile memory arrays are NAND configured flash memory for retention of long term data that has a low number of program and erase cycles.

6. The combination volatile and nonvolatile memory integrated circuit of claim 5 wherein the long term data is selected from the set of data types consisting of application program data, biometric identification information data, and other digital data not requiring a high rate of modification.

7. The combination volatile and nonvolatile memory integrated circuit of claim 1 wherein any of the plurality of the nonvolatile memory arrays are three transistor NAND configured electrically erasable programmable read only memories for retention of shorter term data that has a high number of program and erase cycles.

8. The combination volatile and nonvolatile memory integrated circuit of claim 7 wherein the shorter term data is selected from the data types consisting of short electronic mail digital data, electronic phone book digital data, and other application and program digital data requiring a high rate of modification.

9. The combination volatile and nonvolatile memory integrated circuit of claim 3 wherein the voltage generator further generates a power supply voltage, a first moderately high positive program voltage, a second moderately high positive program voltage, an intermediate positive program voltage, and a ground reference voltage.

10. The combination volatile and nonvolatile memory integrated circuit of claim 5 wherein one of said nonvolatile memory arrays is the NAND configured flash memory and programming the selected first sub-arrays by setting at least one bit line of said selected first sub-arrays to the second moderately high positive program voltage, at least one word line of said selected first sub-arrays to the very large positive programming voltage, at least one source line of said selected first sub-arrays to the second moderately high positive program voltage, and a bulk region of all cells of said selected first sub-array to the ground reference voltage.

11. The combination volatile and nonvolatile memory integrated circuit of claim 7 wherein one of said nonvolatile memory arrays is the three transistor NAND configured electrically erasable programmable read only memories and programming the selected first sub-arrays by setting at least one bit line of said selected first sub-arrays to the ground reference, at least one first select gate line of said selected sub-arrays to the power supply voltage, at least one second select gate line of said selected sub-arrays to the ground reference voltage, at least one word line of said selected first sub-arrays to the very large positive programming voltage, at least one source line of said selected first sub-arrays to the ground reference voltage, and a bulk region of all cells of said selected first sub-array to the ground reference voltage.

12. The combination volatile and nonvolatile memory integrated circuit of claim 11 wherein those cells of said selected first sub-arrays not programmed but have the word line at the very large positive programming voltage are inhibited from programming by setting bit lines of non-selected cells of said selected sub-arrays to the power supply voltage.

13. The combination volatile and nonvolatile memory integrated circuit of claim 11 wherein said very large positive programming voltage is generated externally to said combination volatile and nonvolatile memory integrated circuit.

14. The combination volatile and nonvolatile memory integrated circuit of claim 11 wherein said large positive programming voltage is from approximately +15.0 to approximately +22.0V.

15. The combination volatile and nonvolatile memory integrated circuit of claim 5 wherein one of said nonvolatile memory arrays is the NAND configured flash memory and erasing the selected second sub-arrays by setting at least one word line of said selected second sub-arrays to the very large negative erasing voltage, very large negative erasing voltage, at least one source line of said selected second sub-arrays, and a bulk region of all cells of said selected second sub-array to the ground reference voltage.

16. The combination volatile and nonvolatile memory integrated circuit of claim 7 wherein one of said nonvolatile memory arrays is the three transistor NAND configured electrically erasable programmable read only memories and erasing the selected second sub-arrays by setting at least one first select gate line and second select gate line of said selected sub-arrays to the power supply voltage, at least one word line of said selected second sub-arrays to the very large negative erasing voltage, at least one bit line of said selected second sub-arrays, at least one source line of said selected second sub-arrays, and a bulk region of all cells of said selected second sub-array to the ground reference voltage.

17. The combination volatile and nonvolatile memory integrated circuit of claim 11 wherein said very large negative erasing voltage is generated externally to said combination volatile and nonvolatile memory integrated circuit.

18. The combination volatile and nonvolatile memory integrated circuit of claim 11 wherein said large negative erasing voltage is from approximately −

15.0 to approximately −

22.0V.

19. The combination volatile and nonvolatile memory integrated circuit of claim 1 wherein data resident within any of said plurality of nonvolatile memories may be transferred to said volatile memory such that said volatile memory acts to retain data selected from the classes of data consisting of operational data, temporary data, and scratch pad data.

20. A smart card for securely providing, receiving, and processing secure digital data, said smart card comprising:

a combination volatile and nonvolatile memory integrated circuit placed on a substrate comprising

at least one volatile memory array placed on said substrate;

a plurality of nonvolatile memory arrays placed on said substrate and having an address associated with said volatile memory array;

a memory control circuit in communication with external circuitry to receive address, command, and data signals, to interpret said address, command, and data signals, and in communication with said volatile memory array and said plurality of nonvolatile memory arrays to transfer said address, command and data signals for reading, writing, programming, and erasing said volatile and nonvolatile memory arrays.

21. The smart card of claim 20 wherein said combination volatile and nonvolatile memory integrated circuit further comprises:

a voltage generator that generates a very large positive programming voltage and a very large negative erasing voltage and is in communication with said nonvolatile memory arrays to transfer said very large positive programming voltage to selected first sub-arrays of said nonvolatile memory arrays for programming said selected first sub-arrays and to transfer said very large negative erasing voltage to selected second sub-arrays of said nonvolatile memory arrays for erasing said selected second sub-arrays.

22. The smart card of claim 20 wherein said volatile memory array is selected from a set of volatile random access memories consisting of a static random access memory, a pseudo static random access memory, and a dynamic random access memory.

23. The smart card of claim 20 wherein any of the plurality of the nonvolatile memory arrays is masked programmed read only memory arrays for retention of permanent unchangeable data.

24. The smart card of claim 20 wherein any of the plurality of the nonvolatile memory arrays is NAND configured flash memory for retention of long term data that has a low number of program and erase cycles.

25. The smart card of claim 24 wherein the long term data is selected from the set of data types consisting of application program data, biometric identification information data, and other digital data not requiring a high rate of modification.

26. The smart card of claim 20 wherein any of the plurality of the nonvolatile memory arrays is three transistor NAND configured electrically erasable programmable read only memories for retention of shorter term data that has a high number of program and erase cycles.

27. The smart card of claim 26 wherein the shorter term data is selected from the data types consisting of short electronic mail digital data, electronic phone book digital data, and other digital data requiring a high rate of modification.

28. The smart card of claim 20 wherein the voltage generator further generates a power supply voltage, a first moderately high positive program voltage, a second moderately high positive program voltage, an intermediate positive program voltage, and a ground reference voltage.

29. The smart card of claim 24 wherein one of said nonvolatile memory arrays is the NAND configured flash memory and programming the selected first sub-arrays by setting at least one bit line of said selected first sub-arrays to the second moderately high positive program voltage, at least one word line of said selected first sub-arrays to the very large positive programming voltage, at least one source line of said selected first sub-arrays to the second moderately high positive program voltage, and a bulk region of all cells of said selected first sub-array to the ground reference voltage.

30. The smart card of claim 26 wherein one of said nonvolatile memory arrays is the three transistor NAND configured electrically erasable programmable read only memories and programming the selected first sub-arrays by setting at least one bit line of said selected first sub-arrays to the ground reference, at least one first select gate line of said selected sub-arrays to the power supply voltage, at least one word line of said selected first sub-arrays to the very large positive programming voltage, at least one source line of said selected first sub-arrays to the ground reference voltage, and a bulk region of all cells of said selected first sub-array to the ground reference voltage.

31. The smart card of claim 28 wherein said very large positive programming voltage is generated externally to said combination volatile and nonvolatile memory integrated circuit.

32. The smart card of claim 28 wherein said very large positive programming voltage is from approximately +15.0 to approximately +22.0V.

33. The smart card of claim 30 wherein those cells of said selected first sub-arrays not programmed but have the word line at the very large positive programming 5 voltage are inhibited from programming by setting bit lines of non-selected cells of said selected sub-arrays to the power supply voltage.

34. The smart card of claim 26 wherein one of said nonvolatile memory arrays is the NAND configured flash memory and erasing the selected second sub-arrays by setting at least one word line of said selected second sub-arrays to the very large negative erasing voltage, and by setting at least one source line of said selected second sub-arrays, and a bulk region of all cells of said selected second sub-array to the ground reference voltage.

35. The smart card of claim 26 wherein one of said nonvolatile memory arrays is the three transistor NAND configured electrically erasable programmable read only memories and erasing the selected second sub-arrays by setting at least one first select gate line and second select gate line of said selected sub-arrays to the power supply voltage, at least one word line of said selected second sub-arrays to the very large negative erasing voltage, at least one bit line of said selected second sub-arrays, at least one source line of said selected second sub-arrays, and a bulk region of all cells of said selected second sub-array to the ground reference voltage.

36. The smart card of claim 34 wherein said very large negative erasing voltage is generated externally to said combination volatile and nonvolatile memory integrated circuit.

37. The smart card of claim 34 wherein said very large negative erasing voltage is from approximately −

15.0 to approximately −

22.0V.

38. The smart card of claim 20 wherein data resident within any of said plurality of nonvolatile memories may be transferred to said volatile memory such that said volatile memory acts to retain data selected from the classes of data consisting of operational data, temporary data, and scratch pad data.