Liquid crystal display device and fabricating method thereof, and thin film patterning method applied thereto

• US 20060138428A1
• Filed: 12/02/2005
• Published: 06/29/2006
• Est. Priority Date: 12/24/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Ji No, Ahn, Byung Chul, Kwack, Hee Young, Lim, Joo Soo
• Granted Patent: US 7,425,508 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10S 438/946 Step and repeat

Abstract

A liquid crystal display device, including: a gate line on a substrate; a data line crossing the gate line with a gate insulating film therebetween to define a pixel area; a thin film transistor connected to the gate line and the data line; a semiconductor pattern which forms a channel of the thin film transistor and overlaps along the data line; a passivation film covering the data line and the thin film transistor; and a pixel electrode on the gate insulating film in a pixel hole of the pixel area that penetrates the passivation film and connected to the thin film transistor, the pixel electrode on an inclined side surface of the passivation film to encompass the pixel hole, to form a border with the passivation film and having a thickness that decreases as it goes up the side surface of the passivation film.

Claims

1. A liquid crystal display device, comprising:

a gate line on a substrate;

a data line crossing the gate line with a gate insulating film therebetween to define a pixel area;

a thin film transistor connected to the gate line and the data line;

a semiconductor pattern which forms a channel of the thin film transistor and overlaps along the data line;

a passivation film covering the data line and the thin film transistor; and

a pixel electrode on the gate insulating film in a pixel hole of the pixel area that penetrates the passivation film and connected to the thin film transistor, the pixel electrode on an inclined side surface of the passivation film to encompass the pixel hole, to form a border with the passivation film and having a thickness that decreases as it goes up the side surface of the passivation film.

2. The device according to claim 1, further comprising:

a storage capacitor where the pixel electrode overlaps the gate line with the gate insulating film therebetween.

3. The device according to claim 1, further comprising:

a storage line crossing the data line and extending across the pixel area; and

a storage capacitor where the storage line overlaps the pixel electrode with the gate insulating film therebetween.

4. The device according to claim 3, wherein the pixel electrode overlaps a part of the gate line.

5. The device according to claim 1, further comprising:

a gate pad connected to the gate line,

wherein the gate pad includes;

a gate pad lower electrode extending from the gate line; and

a gate pad upper electrode in a contact hole and connected to the gate pad lower electrode, the contact hole penetrating the passivation film and the gate insulating film.

6. The device according to claim 1, further comprising:

a data pad connected to the data line,

wherein the data pad includes;

a data pad lower electrode extending from the data line together with the semiconductor pattern; and

a data pad upper electrode in a contact hole and connected to the data pad lower electrode, the contact hole penetrating the passivation film.

7. The device according to claim 5, wherein the gate pad upper electrode is on a side surface of the passivation film to encompass the corresponding contact hole, to form a border with the passivation film and has a thickness that decreases as it goes up the side surface of the passivation film.

8. The device according to claim 7, wherein the side surface of the passivation film has a tilt angle of about 15°

-45°

.

9. The device according to claim 6, wherein the data pad upper electrode is on a side surface of the passivation film to encompass the corresponding contact hole to form a border with the passivation film, and has a thickness that decreases as it goes up the side surface of the passivation film.

10. The device according to claim 9, wherein the side surface of the passivation film has a tilt angle of about 15°

-45°

.

11. A liquid crystal display device, comprising:

a gate line and a data line crossing each other with a gate insulating film therebetween to define a pixel area;

a thin film transistor connected to the gate line and the data line;

a pixel electrode on the gate insulating film of the pixel area connected to the thin film transistor; and

a passivation film on the gate insulating film except where the pixel electrode is formed to form a border with the pixel electrode.

12. A method of fabricating a liquid crystal display device, comprising:

a first mask process of forming a gate line on a substrate and a gate electrode connected to the gate line;

a second mask process of forming a gate insulating film covering the gate line and the gate electrode, a semiconductor pattern on the gate insulating film, a data line crossing the gate line on the semiconductor pattern to define a pixel area, a source electrode connected to the data line, and a drain electrode facing the source electrode; and

a third mask process of forming a passivation film covering the data line, the source electrode and the drain electrode, and forming a pixel hole which penetrates the passivation film in the pixel area and forming a pixel electrode connected to the drain electrode in the pixel hole,

wherein the pixel electrode formed on a side surface of the passivation film to encompass the pixel hole, to form a border with the passivation film, and having its thickness decrease as it goes up on the side surface of the passivation film.

13. The method according to claim 12, wherein the third mask process further includes:

forming a photo-resist pattern on the passivation film;

forming a transparent conductive film covering the photo-resist pattern; and

removing a photo-resist pattern where the transparent conductive film is formed,

wherein forming the pixel hole includes forming the pixel hole by wet-etching the passivation film using the photo-resist pattern as a mask, and

forming the photo-resist pattern includes forming the pixel electrode separated from the transparent conductive film in the pixel hole.

14. The method according to claim 12, wherein the third mask process further includes:

forming a storage capacitor by overlapping the pixel electrode with the gate line with the gate insulating film therebetween.

15. The method according to claim 12, wherein the first mask process further includes:

forming a storage line substantially parallel to the gate line on the substrate, and

wherein the third mask process further includes;

forming a storage capacitor by overlapping the pixel electrode with the storage line with the gate insulating film therebetween.

16. The method according to claim 12, wherein the first mask process further includes:

forming a gate pad lower electrode extending from the gate line,

and

wherein the third mask process further includes;

forming a first contact hole penetrating the passivation film and the gate insulating film; and

forming a gate pad upper electrode in the first contact hole connected to the gate pad lower electrode.

17. The method according to claim 16, wherein the second mask process further includes:

forming a data pad lower electrode extending from the data line together with the semiconductor pattern,

and

wherein the third mask process further includes;

forming a second contact hole penetrating the passivation film; and

forming a data pad upper electrode in the second contact hole to be connected to the data pad lower electrode.

18. The method according to claim 17, wherein the third mask process further includes:

forming a photo-resist pattern on the passivation film with a different thickness by a photolithography process using one of a diffractive exposure mask and a halftone mask;

forming the pixel hole and the first and second contact holes using an etching process and the photo-resist pattern with the different thickness as a mask;

forming a transparent conductive film covering the photo-resist pattern, and forming the pixel electrode, the gate pad upper electrode and the data pad upper electrode, which are separated from the transparent conductive film, in the pixel hole and the first and second contact holes; and

removing the photo-resist pattern over which the transparent conductive film is formed.

19. The method according to claim 18, wherein the passivation film where the pixel hole and the first and second contact holes are formed is over-etched versus the photo-resist pattern.

20. The method according to claim 18, wherein the side surface of the passivation film where the pixel hole and the first and second contact holes are formed is over-etched in a horizontal direction beyond an edge of the photo-resist pattern.

21. The method according to claim 18, wherein forming the pixel hole and the first and second contact holes includes:

forming the first contact hole by a first etching process using the photo-resist pattern as a mask; and

forming the pixel hole and the second contact hole by a second etching process using the photo-resist pattern as a mask.

22. The method according to claim 21, wherein dry etching is used in the first etching process and a wet etching is used in the second etching process.

23. The method according to claim 21, wherein the side surface of the passivation film where the pixel hole and the first and second contact holes are formed has a gentle tilt angle.

24. The method according to claim 23, wherein the side surface of the passivation film is formed to have a tilt angle of about 15°

-45°

.

25. The method according to claim 18, wherein the gate pad upper electrode and the data pad upper electrode are formed as far as the side surface of the passivation film, which encompasses the corresponding contact hole, to form a border with the passivation film and the thickness of the pad upper electrode decreases as it goes up the side surface of the passivation film.

26. A method of fabricating a liquid crystal display device, comprising:

forming a gate line and a data line crossing each other with a gate insulating film therebetween to define a pixel area, and a thin film transistor connected to the gate line and the data line;

forming a passivation film on the substrate;

forming a photo-resist pattern on the passivation film;

patterning the passivation film by a wet etching using the photo-resist pattern as a mask;

forming a transparent conductive film on the substrate; and

forming a pixel electrode by patterning the transparent conductive film by removing the photo-resist pattern where the transparent conductive film is formed, wherein the pixel electrode is formed on the gate insulating film and connected to the thin film transistor.

27. A method of patterning thin films, comprising:

forming a first thin film on a substrate;

forming a photo-resist pattern on the first thin film;

over-etching the exposed first thin film through the photo-resist pattern by a wet etching;

forming a second thin film covering the photo-resist pattern; and

patterning the second thin film by removing the photo-resist pattern where the second thin film is formed.

28. The method according to claim 27, wherein each of the first and second thin films includes at least one of an insulating film and a conductive layer.