Semiconductor device having trench gate structure and manufacturing method thereof

• US 20060138535A1
• Filed: 02/27/2006
• Published: 06/29/2006
• Est. Priority Date: 08/05/2003
• Status: Abandoned Application

• Current Assignee: Akio Nakagawa, Syotaro Ono, Yusuke Kawaguchi
• Original Assignee: Akio Nakagawa, Syotaro Ono, Yusuke Kawaguchi
• Inventors: Kawaguchi, Yusuke, Nakagawa, Akio, Ono, Syotaro
• Application Number:
  US11/362,150
• Publication Number:
  US 20060138535A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming a second semiconductor layer of a second conductivity type on a first semiconductor layer of a first conductivity type;

forming a trench which extends from the surface of the second semiconductor layer, penetrates the second semiconductor layer and has depth to reach at least a portion lying near the first semiconductor layer;

forming an insulating film on side walls and a bottom portion of the trench;

forming a third semiconductor layer of the first conductivity type in the first semiconductor layer near the bottom of the trench, the third semiconductor layer having an impurity concentration higher than that of the first semiconductor layer;

forming a fourth semiconductor layer of the second conductivity type by ion-implantating using the third semiconductor layer as a stopper in a region deeper than the second semiconductor layer; and

forming a gate electrode at least partly on the insulating film in the trench.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the forming the second semiconductor layer includes forming a first peak by performing a first ion-implantation process, and the forming the fourth semiconductor layer includes forming a second peak by selecting acceleration voltage higher than that used in the first ion-implantation process and performing a second ion-implantation process.

3. The method of manufacturing a semiconductor device according to claim 1, wherein the second and the fourth semiconductor layers are formed as a base layer.

4. The method of manufacturing a semiconductor device according to claim 2, wherein the first peak and the second peak are formed along and directly face a side surface of the trench.

5. The method of manufacturing a semiconductor device according to claim 2, further comprising forming a source region in the second semiconductor layer, and the first peak is formed in a portion near an interface between the source region and second semiconductor layer, and the second peak is formed in a portion near an interface between the third and the fourth semiconductor layers.

6. The method of manufacturing a semiconductor device according to claim 5, wherein the first peak determines a threshold voltage, and the second peak determines a dose amount of the impurities.

7. The method of manufacturing a semiconductor device according to claim 2, wherein the second peak is lower than the first peak.

8. The method of manufacturing a semiconductor device according to claim 1, further comprising increasing a film thickness of the insulating film on the bottom portion of the trench, after forming the fourth semiconductor layer.

9. The method of manufacturing a semiconductor device according to claim 1, wherein the forming a source region is performed before forming the trench.

10. The method of manufacturing a semiconductor device according to claim 1, wherein the forming a source region is performed after forming the trench.

11. The method of manufacturing a semiconductor device according to claim 9, further comprising forming a fifth semiconductor layer of the second conductivity type in the second semiconductor layer which is adjacent to the source region, after forming the source region.

12. The method of manufacturing a semiconductor device according to claim 10, further comprising forming a fifth semiconductor layer of the second conductivity type in the second semiconductor layer which is adjacent to the source region, after forming the source region.

13. The method of manufacturing a semiconductor device according to claim 1, wherein forming the fourth semiconductor layer includes a thermal diffusion after the ion-implanting.

14. A method of manufacturing a semiconductor device comprising:

forming a first semiconductor layer of a first conductivity type;

forming a first part of a base layer of a second conductivity type in the first semiconductor layer;

forming a trench in the first and the second semiconductor layers;

forming an insulating film on side walls and a bottom portion of the trench;

forming a second semiconductor layer of the first conductivity type in the first semiconductor layer near the bottom of the trench, the second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer;

forming a second part of the base layer of the second conductivity type in the first semiconductor layer using the second semiconductor layer as a stopper in a region deeper than the first part of the base layer; and

forming a gate electrode at least partly on the insulating film in the trench,

wherein the base layer is formed by performing ion-implantation a plurality of times before and after forming the second semiconductor layer.

15. The method of manufacturing a semiconductor device according to claim 14, further comprising forming a third semiconductor layer of the first conductivity type in the first part of the base layer, before forming the trench.

16. The method of manufacturing a semiconductor device according to claim 14, further comprising forming a source region in the first part of the base layer, after forming the second part of the base layer.

17. The method of manufacturing a semiconductor device according to claim 15, further comprising forming a fourth semiconductor layer of the second conductivity type in the first part of the base layer which is adjacent to the source region, after forming the source region.

18. The method of manufacturing a semiconductor device according to claim 16, further comprising forming a fourth semiconductor layer of the second conductivity type in the first part of the base layer which is adjacent to the source region, after forming the source region.

19. The method of manufacturing a semiconductor device according to claim 14, wherein the forming the first and the second parts of the base layer includes a thermal diffusion.