Semiconductor device and method of manufacturing same

• US 20060138541A1
• Filed: 02/24/2006
• Published: 06/29/2006
• Est. Priority Date: 09/24/2003
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Shimamune, Yosuke, Nakamura, Shunji
• Application Number:
  US11/360,775
• Publication Number:
  US 20060138541A1
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78639 with a drain or source connected to a bulk conducting substrate
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A high-speed, low-power-consumption semiconductor device has a thin-film Si layer with a source/drain formed therein. The thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain. The curved thin-film Si layer develops strains in a channel region disposed directly below the gate electrode sandwiched by the source/drain in the thin-film Si layer, for thereby increasing a carrier mobility. A cavity is defined below the curved thin-film Si layer for reducing a parasitic capacitance due to a pn junction.

Claims

1. A semiconductor device having a gate electrode formed on a semiconductor layer with a gate insulating film interposed therebetween and a source/drain formed in the semiconductor layer, said semiconductor layer being curved from a region directly below said gate electrode sandwiched by said source/drain toward a region near said source/drain.

2. The semiconductor device according to claim 1, wherein said region directly below said gate electrode is strained by the curved semiconductor layer.

3. The semiconductor device according to claim 1, wherein a cavity is defined below said source/drain formed in the semiconductor layer and below the region directly below said gate electrode sandwiched by said source/drain.

4. The semiconductor device according to claim 1, wherein an insulating film is formed below said source/drain formed in the semiconductor layer and below the region directly below said gate electrode sandwiched by said source/drain.

5. The semiconductor device according to claim 1, wherein said source/drain is of a stacked source/drain structure comprising another semiconductor layer formed on said semiconductor layer to provide a thick film and an impurity subsequently introduced into the thick film.

6. A method of manufacturing a semiconductor device having a gate electrode formed on a semiconductor layer with a gate insulating film interposed therebetween and a source/drain formed in the semiconductor layer, comprising the steps of:

forming a laminated region of a sacrificial layer and a semiconductor layer and a device separating region surrounding said laminated region, on a substrate;

forming a gate electrode on said device separating region and said semiconductor layer with a gate insulating film interposed therebetween;

forming a source/drain in said semiconductor layer in sandwiching relation to a region directly below said gate electrode;

forming an interlayer insulating film on the entire surface;

forming a contact hole extending through said interlayer insulating film; and

removing said sacrificial layer through said contact hole to form a cavity below said semiconductor layer.

7. The method according to claim 6, wherein said step of forming the contact hole extending through said interlayer insulating film comprises the step of forming the contact hole extending through said interlayer insulating film to said sacrificial layer, further comprising the step of:

after said step of removing said sacrificial layer through said contact hole, forming an impurity diffusion layer in a region directly below said contact hole.

8. The method according to claim 6, further comprising the steps of:

after said step of the source/drain in said semiconductor layer, silicidizing said source/drain entirely,

wherein said interlayer insulating film is formed on the entire surface after said step of silicidizing said source/drain entirely,

wherein said step of forming the contact hole comprises the step of forming the contact hole extending through said interlayer insulating film to said silicidized source/drain, and

wherein said step of removing said sacrificial layer through said contact hole to form said cavity below said semiconductor layer comprises the step of removing said sacrificial layer through said contact hole and said silicidized source/drain to form said cavity below said semiconductor layer.

9. The method according to claim 6, further comprising the step of:

after said step of removing said sacrificial layer through said contact hole to form said cavity below said semiconductor layer, processing a surface of said substrate according to wet etching.