Voltage regulator

• US 20060138546A1
• Filed: 12/22/2005
• Published: 06/29/2006
• Est. Priority Date: 12/22/2004
• Status: Active Grant

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Morino, Koichi, Negoro, Takaaki
• Granted Patent: US 7,394,307 B2
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence

Abstract

A voltage regulator having a MOS transistor driver is disclosed. The voltage regulator comprises a p-channel MOS transistor at a voltage input terminal Vin and a p-channel MOS transistor at a voltage output terminal Vout. A drain of the input side p-channel MOS transistor is connected to the voltage input terminal Vin. A threshold voltage or a voltage lower than the threshold voltage is applied to a gate of the input side p-channel MOS transistor. A drain of the output side p-channel MOS transistor is connected to the voltage output terminal Vout. A current flowing through the input side p-channel MOS transistor drives a voltage regulator circuit and the output side p-channel MOS transistor.

Claims

1. A voltage regulator having a voltage input terminal and a voltage output terminal, comprising:

a first p-channel MOS transistor and a second p-channel MOS transistor connected in series between the voltage input terminal and the voltage output terminal, the first p-channel MOS transistor having a drain connected to the voltage input terminal and a gate to which a threshold or lower voltage is applied, the second p-channel MOS transistor having a drain connected to the voltage output terminal; and

a voltage regulator circuit comprising an operational amplifier, a reference voltage circuit, and a resistance voltage divider;

wherein the voltage regulator circuit and the second p-channel MOS transistor are driven by a current flowing through the first p-channel MOS transistor.

2. The voltage regulator as claimed in claim 1, further comprising:

a cut-off circuit including an equalizer that equalizes gate and source voltages of the first p-channel MOS transistor to stop a current from the voltage output terminal to the voltage input terminal when a voltage at the voltage output terminal is higher than a voltage at the voltage input terminal.

3. The voltage regulator as claimed in claim 1, further comprising:

a signal input terminal; and

a third p-channel MOS transistor disposed at the signal input terminal and having a drain connected to the signal input terminal.

4. The voltage regulator as claimed in claim 1, wherein:

the first p-channel MOS transistor has a current driving power stronger than a current driving power of the second p-channel MOS transistor.

5. The voltage regulator as claimed in claim 2, wherein:

the equalizer is formed by a comparator and an inverter; and

the voltage regulator further comprises a MOS transistor switch connected between a ground and the resistance voltage divider for stopping any circuit other than the comparator.

6. The voltage regulator as claimed in claim 5, wherein:

the inverter is formed by complementary p-channel and n-channel MOS transistors.

7. The voltage regulator as claimed in claim 5, wherein:

the inverter is formed by a p-channel MOS transistor and a constant current circuit.

8. The voltage regulator as claimed in claim 5, wherein:

the inverter is formed by a p-channel MOS transistor and a resistor.