Nonplanar transistors with metal gate electrodes

• US 20060138552A1
• Filed: 02/22/2006
• Published: 06/29/2006
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Mark Doczy, Robert S. Chau, Uday Shah
• Inventors: Shah, Uday, Chau, Robert S., Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Doczy, Mark
• Granted Patent: US 7,531,437 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: Y10S 438/926 Dummy metallization
• CPC Class Codes: Y10S 438/974 Substrate surface preparation

Abstract

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A CMOS integrated circuit comprising:

a PMOS device having an n channel region with a first dopant concentration and a pair of p type source/drain regions having a second dopant concentration and a gate electrode having a first material composition; and

an NMOS device having a p type channel region with a third dopant concentration and a pair of n type source/drain regions having a fourth dopant concentration and a gate electrode comprising said first composition, wherein said first dopant concentration and second dopant concentration and said third dopant concentration and said fourth dopant concentration are such that the threshold voltage for said gate electrode for said p type device is between 0.9-1.1 eV greater than the threshold voltage of the gate electrode for said NMOS device.

2. The CMOS integrated circuit of claim 1 wherein said first dopant concentration is between intrinsic and 4×

10¹⁹ atoms/cm³, said second dopant concentration is between 1×

10¹⁹-1×

10²¹ atoms/cm³, said third dopant concentration is between intrinsic and 4×

10¹⁹ atoms/cm³, and said fourth dopant concentration is between 1×

10¹⁹-1×

10²¹ atoms/cm³.

3. The CMOS integrated circuit of claim 1 wherein said PMOS gate electrode and said NMOS gate electrode comprise a midgap work function material.

4. The CMOS integrated circuit of claim 3 wherein said midgap work function material is selected from the group consisting of the carbides or nitrides of titanium or tantalum.

5. A CMOS integrated circuit comprising:

a p type nonplanar semiconductor device comprising a gate electrode formed from a first film stack formed over and around an n type semiconductor body defining the channel region, said channel region having a first doping concentration and a pair of p type source/drain regions on opposite sides of said gate electrode, said pair of source/drain regions comprising a source/drain extension region and a source/drain contact region;

an n type nonplanar semiconductor device a gate electrode formed from said first film stack formed over and around a p type semiconductor body defining a channel region having a p type conductivity of the first concentration and a pair of n type source/drain regions on opposite sides of said gate electrode, said pair of n type source/drain regions comprising source/drain extension region and a source/drain contact region; and

wherein the doping of said n type source/drain extension regions and said p type channel region of said n type nonplanar semiconductor device and said doping of said p type source/drain extension regions and said n type channel region of said PMOS device create an 0.9-1.1 eV difference in the threshold voltage of said gate electrode of said p type semiconductor device and said gate electrode of said n type semiconductor device.

6. The CMOS integrated circuit of claim 5 wherein said n type channel region has a doping concentration between intrinsic and 4×

10¹⁹ atoms/cm³ and said p type source/drain regions extension regions have a doping concentration between 1×

10¹⁹-1×

10²¹ atoms/cm³ and said p type channel region having a doping concentration between intrinsic and 4×

10¹⁹ atoms/cm³ and said n type source/drain extension regions have doping concentration between 1×

10¹⁹-1×

10²¹ atoms/cm³.

7. The CMOS integrated circuit of claim 5 wherein said PMOS gate electrode and said NMOS gate electrode are each formed from material having a midgap work function.

8. A method of forming a CMOS integrated circuit:

forming a PMOS device having a gate electrode formed from a first material and forming an NMOS device having a gate electrode formed from said first material; and

forming a channel region and a source/drain region for said PMOS device and a channel region and a source/drain region for said NMOS device such that the threshold voltage of said gate electrode for said PMOS device is about 0.9-1.1 eV greater than the threshold voltage of said gate electrode for said NMOS device.

9. The method of claim 8 wherein said first material has midgap work function.

10. The method of claim 9 wherein said first material has a work function between 4.3-4.8 eV.

11. The method of claim 8 wherein channel region of said PMOS device is n type silicon and the channel region for said NMOS device is p type silicon.

12. The method of claim 8 wherein said first material comprises a lower metal film and an upper metal film.

13. The method of claim 12 wherein said lower metal film sets the work function for said material.

14. The method of claim 13 wherein said lower metal film is selected from the group consisting of the carbides or nitrides of titanium or tantalum.

15. A method of forming a semiconductor device comprising:

forming a sacrificial gate electrode material and a hard mask material over a semiconductor body;

patterning said sacrificial gate electrode material and said hard mask material into a hard mask and a sacrificial gate electrode;

forming a dielectric layer over and around said sacrificial gate electrode and said hard mask;

planarizing said dielectric layer until said hard mask is exposed and said dielectric layer is substantially planar with the top surface of said hard mask;

etching away said hard mask to reveal said sacrificial gate electrode;

etching away said sacrificial gate electrode to form an opening in said dielectric layer to expose said channel region of said semiconductor body;

depositing a gate dielectric layer over and around said channel region of said semiconductor body in said opening and on said top surface of said planarized interlayer dielectric;

blanket depositing a gate electrode material on said gate dielectric layer in said opening and on said gate dielectric layer on said dielectric layer; and

polishing said gate electrode material on said gate dielectric layer until said gate electrode material and said gate dielectric layer are completely removed from the top surface of said dielectric layer to form a gate electrode and a gate dielectric layer.

16. The method of claim 15 wherein said gate electrode material comprises a lower film having a midgap work function and an upper metal film.

17. The method of claim 16 wherein said midgap work function material is selected from the group consisting of the carbides or nitrides of titanium or tantalum.

18. The method of claim 15 wherein said fill metal is selected from the group consisting of copper and tungsten.

19. The method of claim 15 further comprising after removing said sacrificial gate electrode material and said hard mask and prior to forming said gate dielectric layer, exposing said channel region of said semiconductor body to a solution which converts said channel region of said semiconductor body into a hydrophilic surface.

20. The method of claim 19 wherein said solution comprising hydrogen peroxide.

21. The method of claim 19 wherein said gate dielectric layer is formed by atomic layer deposition.

22. The method of claim 21 wherein said atomic layer deposition comprises exposing said hydrophilic surface of said semiconductor body to a metal halide.

23. The method of claim 22 wherein said metal halide is hafnium tetrachloride (HfCl₄).

24. The method of claim 15 further comprising forming a pair of sidewall spacers adjacent to said hard mask and said sacrificial gate electrode, said sidewall spacers having a top surface above the top surface of said sacrificial gate electrode and below the top surface of said hard mask.

25. The method of claim 24 wherein said semiconductor body has a height less than the thickness of said hard mask.

26. The method of claim 25 further comprising forming silicon on the top surface and sidewalls of said semiconductor body adjacent to the outside edges of said sidewall spacers.

27. The method of claim 26 further comprising forming silicide on said silicon film formed on the top surface and sidewalls of said semiconductor body.

28. The method of claim 24 wherein said sacrificial gate electrode comprises polysilicon.

29. The method of claim 24 wherein said sidewall spacers are formed by a method comprising:

blanket comprising a conformal dielectric layer over said sidewalls of said sacrificial gate electrode, and on the top surface of said hard mask, and onto the sidewalls in the top surface of said semiconductor body; and

anisotropically etching back said conformal dielectric layer so that said conformal dielectric layer is removed from the top surface of said hard mask and the top surface of said semiconductor body, and continuing said anisotropic etch back until said conformal dielectric layer is removed from the sidewalls of said semiconductor body.

30. A method of forming a transistor comprising:

forming a polysilicon sacrificial gate electrode having a pair of laterally opposite sidewalls and a hard mask formed on the top surface of said polysilicon gate electrode, said sacrificial gate electrode formed over a channel region of a semiconductor body having the top surface and pair of laterally opposite sidewalls;

blanket depositing a spacer dielectric layer over said hard mask and on said pair of laterally opposite sidewalls of said sacrificial gate electrode and on said sidewalls and top surface of said semiconductor body;

anisotropically etching back said spacer dielectric layer so that said spacer dielectric layer is removed from the top surface of said hard mask and the top surface of said semiconductor body, and continuing said anistropic etch back until said spacer dielectric layer is removed from the semiconductor body so that a pair of sidewall spacers are formed adjacent to said sidewalls of said sacrificial polysilicon gate electrode and adjacent to a portion of said hard mask on said top surface of said polysilicon sacrificial gate electrode.

31. The method of claim 30 further comprising forming silicon onto the sidewalls and top surface of said semiconductor body adjacent to said sidewall spacers.

32. The method of claim 31 further comprising forming silicide on said silicon film formed on the top surface and sidewalls of said semiconductor body.

33. The method of claim 32 wherein said silicide is formed by a method comprising:

blanket depositing a metal film over said sidewall spacers and said hard mask as well as onto said silicon film formed on said sidewalls and top surface of said semiconductor body;

heating said metal film so that said metal film reacts with said silicon film formed on said semiconductor body to form a silicide film adjacent to the sidewalls and above the top surface of said semiconductor body, wherein said metal film does not react with said sidewalls spacers or said hard mask and wherein said sidewall spacers and said hard mask prevent said metal film from reacting with said polycrystalline sacrificial gate electrode; and

etching away said unreacted metal film from said hard mask and from said sidewall spacers.

34. A method of forming a metal oxide gate dielectric layer comprising:

exposing a silicon surface to a solution which makes said silicon surface hydrophilic;

exposing said hydrophilic silicon surface to a precursor comprising a metal halide; and

forming a metal oxide dielectric layer by reacting said metal halide with said hydrophilic surface.

35. The method of claim 34 wherein said hydrophilic silicon surface comprises an OH terminated silicon atom.

36. The method of claim 34 wherein said solution comprises hydrogen peroxide.

37. The method of claim 36 wherein said solution comprises between 5-10% hydrogen peroxide by volume in water.

38. The method of claim 34 wherein said metal oxide dielectric is selected from the group consisting of hafnium oxide, aluminum oxide, zirconium oxide, lanthanum oxide, and lanthanum aluminum oxide.

39. The method of claim 38 wherein said metal oxide dielectric comprise hafnium oxide.

40. The method of claim 39 wherein said metal halide comprises hafnium tetrafluoride (HfCl₄).

41. A method of forming a high dielectric constant film on a silicon surface comprising:

removing a silicon oxide film from a silicon surface with an aqueous HF solution to generate a hydrophobic silicon hydride surface;

treating said hydrophobic silicon hydride surface with a solution comprising hydrogen peroxide to convert said hydrophobic silicon hydride surface to a hydrophilic silicon hydroxide surface;

exposing said hydrophilic silicon hydroxide surface to a metal halide to form a metal halide terminated silicon surface; and

exposing said metal halide terminated silicon surface to water vapor to form a metal oxide dielectric film on said silicon surface.

42. The method of claim of claim 41 wherein said aqueous HF solution comprises approximately 1-2% HF by volume in water.

43. The method of claim 41 wherein said solution comprising hydrogen perioxide comprises 5-10% by weight of unstabilized hydrogen peroxide in water.

44. The method of claim 41 wherein said metal halide is selected from the group consisting of HfCl₄, ZrCl₄ and LaCl₃.

45. The method of claim 41 wherein said hydrophilic silicon hydroxide surface is exposed to a metal halide at a temperature between 350-450°

C.

46. The method of claim 41 further comprising after forming said metal oxide dielectric, exposing said metal oxide dielectric to said metal halide a second time and exposing said metal oxide to said water vapor a second time.

47. A method of forming a CMOS integrated circuit comprising:

forming a first sacrificial gate electrode over an n type semiconductor channel region;

forming a second sacrificial gate electrode over a p type semiconductor channel region;

forming a dielectric layer over said first and said second sacrificial gate electrode;

planarizing said dielectric layer;

revealing the top surface of said first and second sacrificial gate electrodes;

removing said first sacrificial gate electrode to form a first opening over said n type channel region and removing said second sacrificial gate electrode to form a second opening over said p type semiconductor channel region;

forming a gate dielectric layer in said first opening on said n type semiconductor channel region and in said second opening on said p type semiconductor channel region;

forming a metal gate electrode material onto said gate dielectric layer in said first opening and onto said gate dielectric layer in second opening and above said planarized dielectric layer; and

polishing said gate electrode material from above said interlayer dielectric to form a first gate electrode over said gate dielectric layer in said opening and a second gate electrode on said gate dielectric layer in said second opening.

48. The method of claim 47 wherein said gate electrode material comprises a lower metal film and an upper metal film.

49. The method of claim 48 wherein said lower metal film comprises a midgap work function material.

50. The method of claim 49 wherein said upper film is selected from the group consisting of copper and tungsten.

51. The method of claim 47 further comprising after forming said first and second gate electrode by polishing, removing said dielectric layer.

52. The method of claim 51 further comprising after removing said dielectric layer, blanket depositing a silicon nitride film on and around said first gate electrode and said second gate electrode.

53. The method of claim 52 further comprising forming a second dielectric layer over said silicon nitride layer.