Nonplanar transistors with metal gate electrodes

• US 20060138553A1
• Filed: 02/24/2006
• Published: 06/29/2006
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Brian S. Doyle, Jack Kavalleros, Justin K. Brask, Mark Doczy, Robert S. Chau, Uday Shah
• Inventors: Shah, Uday, Chau, Robert S., Doyle, Brian S., Brask, Justin K., Doczy, Mark, Kavalleros, Jack
• Granted Patent: US 7,326,656 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: Y10S 438/926 Dummy metallization
• CPC Class Codes: Y10S 438/974 Substrate surface preparation

Abstract

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1-33. -33. (canceled)

34. A method of forming a metal oxide gate dielectric layer comprising:

exposing a silicon surface to a solution which makes said silicon surface hydrophilic;

exposing said hydrophilic silicon surface to a precursor comprising a metal halide; and

forming a metal oxide dielectric layer by reacting said metal halide with said hydrophilic surface.

35. The method of claim 34 wherein said hydrophilic silicon surface comprises an OH terminated silicon atom.

36. The method of claim 34 wherein said solution comprises hydrogen peroxide.

37. The method of claim 36 wherein said solution comprises between 5-10% hydrogen peroxide by volume in water.

38. The method of claim 34 wherein said metal oxide dielectric is selected from the group consisting of hafnium oxide, aluminum oxide, zirconium oxide, lanthanum oxide, and lanthanum aluminum oxide.

39. The method of claim 38 wherein said metal oxide dielectric comprise hafnium oxide.

40. The method of claim 39 wherein said metal halide comprises hafnium tetrafluoride (HfCl₄).

41. A method of forming a high dielectric constant film on a silicon surface comprising:

removing a silicon oxide film from a silicon surface with an aqueous HF solution to generate a hydrophobic silicon hydride surface;

treating said hydrophobic silicon hydride surface with a solution comprising hydrogen peroxide to convert said hydrophobic silicon hydride surface to a hydrophilic silicon hydroxide surface;

exposing said hydrophilic silicon hydroxide surface to a metal halide to form a metal halide terminated silicon surface; and

exposing said metal halide terminated silicon surface to water vapor to form a metal oxide dielectric film on said silicon surface.

42. The method of claim of claim 41 wherein said aqueous HF solution comprises approximately 1-2% HF by volume in water.

43. The method of claim 41 wherein said solution comprising hydrogen perioxide comprises 5-10% by weight of unstabilized hydrogen peroxide in water.

44. The method of claim 41 wherein said metal halide is selected from the group consisting of HfCl₄, ZrCl₄ and LaCl₃.

45. The method of claim 41 wherein said hydrophilic silicon hydroxide surface is exposed to a metal halide at a temperature between 350-450°

C.

46. The method of claim 41 further comprising after forming said metal oxide dielectric, exposing said metal oxide dielectric to said metal halide a second dtime and exposing said metal oxide to said water vapor a second time.

47. A method of forming a CMOS integrated circuit comprising:

forming a first sacrificial gate electrode over an n type semiconductor channel region;

forming a second sacrificial gate electrode over a p type semiconductor channel region;

forming a dielectric layer over said first and said second sacrificial gate electrode;

planarizing said dielectric layer;

revealing the top surface of said first and second sacrificial gate electrodes;

removing said first sacrificial gate electrode to form a first opening over said n type channel region and removing said second sacrificial gate electrode to form a second opening over said p type semiconductor channel region;

forming a gate dielectric layer in said first opening on said n type semiconductor channel region and in said second opening on said p type semiconductor channel region;

forming a metal gate electrode material onto said gate dielectric layer in said first opening and onto said gate dielectric layer in second opening and above said planarized dielectric layer; and

polishing said gate electrode material from above said interlayer dielectric to form a first gate electrode over said gate dielectric layer in said opening and a second gate electrode on said gate dielectric layer in said second opening.

48. The method of claim 47 wherein said gate electrode material comprises a lower metal film and an upper metal film.

49. The method of claim 48 wherein said lower metal film comprises a midgap work function material.

50. The method of claim 49 wherein said upper film is selected from the group consisting of copper and tungsten.

51. The method of claim 47 further comprising after forming said first and second gate electrode by polishing, removing said dielectric layer.

52. The method of claim 51 further comprising after removing said dielectric layer, blanket depositing a silicon nitride film on and around said first gate electrode and said second gate electrode.

53. The method of claim 52 further comprising forming a second dielectric layer over said silicon nitride layer.