Power core devices and methods of making thereof

• US 20060138591A1
• Filed: 11/30/2005
• Published: 06/29/2006
• Est. Priority Date: 12/21/2004
• Status: Active Grant

• Current Assignee: Chemtron Research LLC (Intellectual Ventures LLC)
• Original Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.)
• Inventors: Sreeram, Attiganal N., Banerji, Sounak, Amey, Daniel Irwin Jr., Borland, William J., McGregor, David Ross, Dietz, Karl Hartmann
• Granted Patent: US 7,613,007 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0355 : Metal foils
• CPC Class Codes: H05K 2201/09309 : Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/09536 : Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/09763 : Printed component having superposed conductors, but integrated in one circuit layer
• CPC Class Codes: H05K 3/429 : Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4641 : having integrally laminated metal sheets or special power cores

Abstract

The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.

Claims

1. A device comprising a power core wherein said power core comprises:

at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and

at least one planar capacitor laminate;

wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said embedded singulated capacitor; and

wherein said embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and

wherein said power core is interconnected to at least one signal layer.

2. The device of claim 1 wherein said power core comprises multiple embedded singulated capacitor layers and multiple planar capacitor laminates.

3. The device of claim 1 wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode.

4. The device of claim 3 wherein the embedded singulated capacitor first electrode and second electrode are connected to at least one power terminal of a semiconductor device.

5. The device of claim 4 wherein said semiconductor device is an integrated circuit.

6. The device of claim 1 comprising more than one signal layer wherein said signal layers are connected through conductive vias.

7. The device of claim 1 wherein said device is selected from an interposer, printed wiring board, multichip module, area array package, system-on-package, and system-in-package.

8. A method for making a device comprising:

providing at least one planar capacitor having a patterned side and a non-patterned side;

providing at least one foil structure comprising at least one formed on foil singulated capacitor having a foil side and a component side; and

laminating said component side of said foil structure to said patterned side of said planar capacitor structure;

etching said foil side of said foil structure and etching said non-patterned side of said planar capacitor structure forming a power core; and

forming at least one signal layer onto said power core.

10. The method of claims 8 or 9 wherein said signal layers are formed by applying a dielectric layer to one or both surfaces of said power core;

forming circuitry comprising one or more signal lines on said dielectric layer; and

forming a conductive interconnection between layers comprising said signal lines.

11. The method of claim 10 wherein said interconnection between layers is a conductive via.

12. The method of any one of claims 8 or 9 wherein additional passive components are connected to and external to said power core.

13. The method of any one of claims 8 or 9 wherein signal lines, resistors, or combinations thereof may be placed and interconnected on the same layer as said singulated capacitors.

9. A method for making a device comprising:

providing at least one planar capacitor having a patterned side and a non-patterned side;

providing at least one foil structure comprising at least one formed on foil singulated capacitor having a foil side and a component side; and

laminating said foil side of said foil structure to said patterned side of said planar capacitor structure etching said foil side of said foil structure and etching said non-patterned side of said planar capacitor structure forming a power core; and

forming at least one signal layer onto said power core.

14. A method for making a device comprising:

providing at least one planar capacitor having a first patterned side and a second patterned side;

providing at least one foil structure comprising at least one formed on foil singulated capacitor having a foil side and a component side; and

laminating said component side of said foil structure to said laminate foil pair;

forming at least one signal layer;

etching said foil side of said foil laminate foil pair;

etching said non-patterned side of said planar capacitor structure; and

laminating to form a device.

15. The method of claim 14 wherein each layer is interconnected to other layers by conductive vias.

16. The method of claim 15 wherein said conductive vias are formed by the methods selected from filling vias with conductive material, plating vias with conductive material, and forming conductive bumps on foil.

17. A method for making a device comprising:

providing at least one planar capacitor having a patterned side and a non-patterned side;

providing at least one foil structure comprising at least one formed on foil singulated capacitor having a foil side and a component side; and

laminating said foil side of said foil structure to said patterned side of said planar capacitor structure;

etching said foil side of said foil structure and etching said non-patterned side of said planar capacitor structure forming a power core;

forming a prefabricated signal line assembly; and

joining said power core and said prefabricated signal line assembly.