Microelectronic packages using a ceramic substrate having a window and a conductive surface region

• US 20060138626A1
• Filed: 12/29/2004
• Published: 06/29/2006
• Est. Priority Date: 12/29/2004
• Status: Abandoned Application

• Current Assignee: Tessera, Inc. (Adeia, Inc.)
• Original Assignee: Tessera, Inc. (Adeia, Inc.)
• Inventors: Liew, Victor, Humpston, Giles
• Application Number:
  US11/025,432
• Publication Number:
  US 20060138626A1
• Time in Patent Office: Days
• US Class Current: 257/684
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A microelectronic package includes a microelectronic device, a unitary ceramic substrate, and a plurality of terminals. The microelectronic device has a front surface and a plurality of electrical contacts thereon. The substrate has first and second opposing surfaces. A window extends from a first opening on the first surface along a side wall to a second opening on the second surface. A conductive region may be provided on the side wall and/or the second substrate surface. The substrate is located between the device and the terminals such that the first surface of the substrate faces the front surface of the device and the first opening is aligned with at least one contact on the front device surface. Also provided are methods for producing microelectronic packages and wafer-scale assemblies.

Claims

1. A microelectronic package, comprising:

a microelectronic device having a substantially planar front surface and a plurality of electrical contacts thereon;

a unitary ceramic substrate having

a first substantially planar surface,

a second surface opposing first surface,

a window having varied cross-sectional areas and extending from a first opening on the first surface along a side wall to a second opening on the second surface, and

a conductive region on the side wall; and

a plurality of terminals,

wherein the substrate is located between the device and the terminals such that the first surface of the substrate faces the front surface of the device and the first opening is aligned with the contacts on the front device surface.

2. The package of claim 1, wherein the device is a memory chip.

3. The package of claim 1, wherein the electrical contacts are located in a central portion of the front device surface.

4. The package of claim 1, wherein the electrical contacts are substantially absent from a peripheral portion of the front device surface.

5. The package of claim 1, wherein the first opening has a smaller cross-sectional area than the second opening.

6. The package of claim 5, wherein the side wall is tapered from the second opening to the first opening.

7. The package of claim 1, wherein the side wall includes a ledge.

8. The package of claim 7, wherein the conductive region is present on the ledge.

9. The package of claim 1, having substantially no void between the first surface of the substrate and the front surface of the device.

10. The package of claim 1, further comprising an adhesive between the device and the substrate.

11. The package of claim 1, further comprising a compliant layer between the device and at least one terminal.

12. The package of claim 11, wherein the compliant layer is located between the at least one terminal and the substrate.

13. The package of claim 11, wherein the compliant layer is located between the device and the substrate.

14. The package of claim 1, wherein at least one device contact is in electrical communication with at least one terminal through the window via the conductive region.

15. The package of claim 14, wherein the at least one device contact is lead bonded or wire bonded to the conductive region.

16. The package of claim 1, comprising different conductive regions on different portions of the side wall, wherein different device contacts are in electrical communication with different terminals through the window via different conductive regions.

17. The package of claim 14, further comprising an encapsulant within the window.

18. The package of claim 17, wherein encapsulant fills the window to a substantially void-free degree.

19. The package of claim 1, wherein the substrate is comprised of an amorphous ceramic material.

20. The package of claim 1, further comprising a recess on the second substrate surface that contains at least one terminal.

21. The package of claim 1, wherein the terminal and the conductive region are comprised of a contiguous coating of substantially uniform composition.

22. The package of claim 21, wherein the contiguous coating is comprised of a metal.

23. The package of claim 21, wherein the contiguous coating has a thickness no greater than about 5 micrometers.

24. The package of claim 23, wherein the thickness of the contiguous coating is no greater than about 3 micrometers.

25. The package of claim 24, wherein the thickness of the contiguous coating is about 0.1 to about 1 micrometer.

26. The package of claim 1, further comprising solder balls and solder resist on the second surface of the substrate.

27. A microelectronic package, comprising:

a microelectronic device having a substantially planar front surface and a plurality of electrical contacts thereon;

a unitary ceramic substrate having

a first substantially planar surface,

a second surface opposing first surface,

a window extending from a first opening on the first surface along a side wall to a second opening on the second surface, and

a metal coating on the side wall and/or the second substrate surface; and

+P2

a plurality of terminals,

wherein the substrate is located between the device and the terminals such that the first surface of the substrate faces the front surface of the device, the first opening is aligned with at least one contact on the front device surface, and the at least one device contact is in electrical communication with at least one terminal through the window via a lead or wire bond to the conductive region.

28. A wafer-scale microelectronic assembly, comprising:

a wafer comprising an array of microelectronic devices each having a coplanar front surface and a plurality of electrical contacts thereon; and

a unitary ceramic substrate having

a first substantially planar surface

a second surface opposing first surface,

a plurality of windows each having varied cross-sectional areas extending from a first opening on the first surface along a side wall to a second opening on the second surface, and

a conductive region on at least a portion of each side wall,

wherein the first surface of the substrate faces the front device surfaces, and each first opening is aligned with electrical contacts on a different device.

29. A wafer-scale microelectronic assembly, comprising:

a wafer comprising an array of microelectronic devices each having a coplanar front surface and a plurality of electrical contacts thereon; and

a unitary ceramic substrate having

a first substantially planar surface

a second surface opposing first surface,

a window having varied cross-sectional areas extending from a first opening on the first surface along a side wall to a second opening on the second surface, and

a conductive region on each side wall,

wherein the first surface of the substrate faces the front surface of the device, and the first opening is aligned with at least one electrical contact on each different device.

30. A wafer-scale microelectronic assembly, comprising:

a wafer having a diameter of at least 200 mm comprising an array of microelectronic devices each having a coplanar front surface and a plurality of electrical contacts thereon; and

a unitary ceramic substrate having

a first substantially planar surface

a second surface opposing first surface, and

a window having varied cross-sectional areas extending from a first opening on the first surface along a side wall to a second opening on the second surface,

wherein the substrate is positioned such that the first surface of the substrate faces the front surface of the device, each first opening is aligned with at least one electrical contact on different device, and the substrate and the device have coefficients of thermal expansion that differs by no more than about 0.1 ppm/°

C.

31. A method for forming a microelectronic package, comprising:

(a) providing

a microelectronic device having a substantially planar front surface and a plurality of electrical contacts thereon, and

a unitary ceramic substrate having a first substantially planar surface, a second surface opposing first surface, a window having varied cross-sectional areas and extending from a first opening on the first surface along a side wall to a second opening on the second surface, and a conductive region on the side wall,

wherein the first surface of the substrate faces the front surface of the device and the first opening is aligned with at least one contact on the front device surface; and

(b) establishing electrical communication between at least one contact and the conductive region through the first opening.

32. The method of claim 31, wherein step (b) comprises lead bonding or wire bonding at least one device contact to the conductive region.

33. The method of claim 31, further comprising step (c) providing a terminal that electrically communicates with the electrically conductive region.

34. The method of claim 33, wherein step (c) is carried out before step (b).

35. The method of claim 33, further comprising, during or after step (b), filling the window with an encapsulant.

36. The method of claim 33, further comprising step (d) establishing electrical communication between the terminal and an external circuit.

37. The method of claim 36, wherein step (b) comprises soldering, lead bonding or wire bonding the terminal to the external circuit.

38. A method for forming a microelectronic assembly, comprising:

(a) providing

a wafer comprising an array of microelectronic device each having a coplanar front surface and a plurality of electrical contacts thereon, and

a unitary ceramic substrate having a first substantially planar surface, a second surface opposing first surface, an array of windows each corresponding to a different microelectronic device, having varied cross-sectional areas, and extending from a first opening on the first surface along a side wall to a second opening on the second surface, and a conductive region on each side wall,

wherein the first surface of the substrate faces the front surfaces of the devices and each first opening is aligned with contacts on the front surface of the corresponding microelectronic device; and

(b) establishing electrical communication between at least one contact for each device and the conductive region on the side wall of the window corresponding to each device, thereby forming a microelectronic assembly.

39. The method of claim 38, further comprising dicing the microelectronic assembly into individual microelectronic packages.