Ic tag

• US 20060139174A1
• Filed: 11/20/2003
• Published: 06/29/2006
• Est. Priority Date: 11/21/2002
• Status: Active Grant

• Current Assignee: Lintec Corporation
• Original Assignee: Lintec Corporation
• Inventors: Yamakage, Masateru, Nakata, Yasukazu, Matsushita, Taiga
• Granted Patent: US 7,294,917 B2
• Time in Patent Office: Days
• US Class Current: 340/572.800
• CPC Class Codes: G06K 19/0739 the incapacitated circuit being part of an antenna
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/0776 the adhering arrangement being a layer of adhesive, so that the record carrier can function as a sticker

Abstract

The present invention provides an IC tag which has a structure comprising a first adhesive layer laminated on a surface of a substrate sheet, an electronic circuit containing a circuit line having a bypass line and an IC chip connecting to the electronic circuit which are formed on a surface of the first adhesive layer, a second adhesive layer laminated for covering the electronic circuit and the IC chip, and a release agent layer formed partly at the position corresponding to a circuit section consisting of the electronic circuit and the IC chip and located at the interface between the substrate sheet and the first adhesive layer, wherein the angle formed by the tangent of the bypass line at the connection between the bypass line and the circuit line and the tangent of the circuit line at the connection is 10 degree or greater. When the IC tag attached to an article is peeled off, the built-in electronic circuit is surely broken.

Claims

1. An IC tag which has a structure comprising a first adhesive layer laminated on a surface of a substrate sheet, an electronic circuit containing a circuit line having a bypass line, in which the angle formed by the tangent of the bypass line at the connection between the bypass line and the circuit line and the tangent of the circuit line at the connection is 10 degree or greater, and an IC chip connecting to the electronic circuit which are formed on a surface of the first adhesive layer, a second adhesive layer laminated for covering the electronic circuit and the IC chip, and a release agent layer formed partly at the position corresponding to a circuit second consisting of the electronic circuit and the IC chip and located at he interface between the substrate sheet and the first adhesive layer.

2. The IC tag as claimed in claim 1, wherein at least one of bypass line is formed at the position in the circuit section in which the release agent layer is formed.

3. The IC tag as claimed in claim 1, wherein a planar projection is extended to the bypass line.

8. The IC tag as claimed in claim 1, wherein the release agent layer is formed to cover the range of 20 to 90 percents of an area surrounded by an outside circumference.

9. The IC tag as claimed in claim 1, wherein a release liner is formed on a surface of the second adhesive layer.

4. An IC tag which has a structure comprising a first adhesive layer laminated on a surface of a substrate sheet, an electronic circuit having a planar projection extended and an IC chip connecting to the electronic circuit which are formed on a surface of the first adhesive layer, a second adhesive layer laminated for covering the electronic circuit and the IC chip, and a release agent layer formed partly at the position corresponding to a circuit section consisting of the electronic circuit and the IC chip and located at the interface between the substrate sheet and the first adhesive layer.

6. The IC tag as claimed in claim 4, wherein at least one of bypass line is formed at the position in the circuit section in which the release agent layer is formed.

7. The IC tag as claimed in claim 4, wherein the planer projection has an are calculated according to the following formula.

S=(SW)²

(In the formula, S is an area of the planar projection, and W is a line width of the circuit line adjoining to the planar projection.)

5. An IC tag which has a structure comprising a first adhesive layer laminated on a surface of a substrate sheet, on electronic circuit having a planer projection extended and an IC chip connecting to the electronic circuit which are formed on a surface of the first adhesive layer, a second adhesive layer laminated for covering the electronic circuit and the IC chip, and a release agent layer formed partly at the position corresponding to both end portions of a circuit section consisting of the electronic circuit and the IC chip and located at eth interface between the substrate sheet and the first adhesive layer.