Device and structure arrangements for integrated circuits and methods for analyzing the same

• US 20060139411A1
• Filed: 12/29/2004
• Published: 06/29/2006
• Est. Priority Date: 12/29/2004
• Status: Active Grant

• Current Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Original Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Inventors: Rowe, Kristi M., Guan, Yimin
• Granted Patent: US 7,296,871 B2
• Time in Patent Office: Days
• US Class Current: 347/59
• CPC Class Codes: B41J 2/14072 Electrical connections, e.g. details on electrodes, connecting the chip to the outside...
• CPC Class Codes: B41J 2/14129 Layer structure

Abstract

An integrated circuit having a plurality of devices. The plurality of devices have a plurality of device characteristics. A sectional cut through the integrated circuit reveals the plurality of device characteristics.

Claims

1. An integrated circuit comprising a plurality of devices having a plurality of device characteristics, the plurality of devices are physically aligned such that a sectional cut through the integrated circuit completely reveals the plurality of device characteristics.

2. The integrated circuit of claim 1, wherein the plurality of devices comprise at least one of a heater, a fuse with spin-on glass (“

SOG”

), a plurality of logic transistors, a plurality of power field-effect transistors, a plurality of ink via, and a plurality of scribes.

3. The integrated circuit of claim 2, wherein the plurality of logic transistors are arranged in a plurality of orientations with respect to the sectional cut.

4. The integrated circuit of claim 2, wherein the plurality of power field-effect transistors are arranged in a plurality of orientations with respect to the sectional cut.

5. The integrated circuit of claim 1, further comprising a plurality of structures arranged adjacent the plurality of devices wherein the sectional cut through the integrated circuit completely reveals a plurality of characteristics of the plurality of structures.

6. The integrated circuit of claim 1, wherein the plurality of device characteristics comprise at least one of a heater length, a heater width, a fuse length, a fuse width, a scribe step coverage, a transistor length, a transistor width, a contact size, a polycrystalline Silicon line width, a polycrystalline Silicon line space, an N-implant depth, a P-implant depth, a lightly-doped drain (“

LDD”

) implant depth, a LDD implant space, an NWELL depth, metal to implant contact width, a contact to polycrystalline Silicon space on an active region, a polycrystalline Silicon spacing, a polycrystalline Silicon line width, metal to metal spacing, metal to metal via, a metal line width, and a metal to metal to polycrystalline Silicon overlap.

7. The integrated circuit of claim 1, wherein the sectional cut comprises a cross sectional cut.

8. A method of structuring devices in an integrated circuit, the integrated circuit having a plurality of locations, the method comprising the acts of:

arranging a plurality of devices of the integrated circuit in close proximity in one of the locations; and

revealing the plurality of devices with a sectional cut on the integrated circuit at the one of the locations.

9. An integrated circuit having a plurality of locations, the integrated circuit comprising a plurality of devices in one of the plurality of locations, wherein the one of the plurality of locations has an area of no greater than 0.5×

10<sup>−

6</sup>m², and wherein the one of the locations is configured to allow a sectional cut to completely reveal a plurality of characteristics of the plurality of devices.

10. The integrated circuit of claim 9, wherein the area is at most 0.08×

10<sup>−

6</sup>m².

11. An integrated circuit having a die area and a plurality of locations, the integrated circuit comprising a plurality of devices in one of the plurality of locations, wherein the one of the plurality of locations has an area of no greater than 1 percent of the die area, and wherein the one of the locations is configured to allow a sectional cut to completely reveal a plurality of characteristics of the plurality of devices.

12. The integrated circuit of claim 11, wherein the area is at most 0.15 percent of the die area.

13. An inkjet printing apparatus comprising a print head having a plurality of locations, and a plurality of devices arranged on one of the plurality of locations, wherein the one of the locations is configured to allow a sectional cut that completely reveals a plurality of characteristics of the plurality of devices.

14. A print head comprising a plurality of devices, the print head having a plurality of locations wherein one of the locations is configured to allow a sectional cut that reveals a plurality of characteristics of the plurality of devices and structures.

15. An integrated circuit comprising a plurality of devices, each of the devices having a plurality of characteristics, the devices are physically oriented to allow sectional cuts made through the circuit to reveal the device characteristics, wherein an amount of the sectional cuts needed to reveal the device characteristics is substantially less than an amount of device characteristics revealed.

16. The integrated circuit of claim 15, wherein the plurality of devices comprise at least one of a heater, a fuse with spin-on glass (“

SOG”

), a plurality of logic transistors, a plurality of power field-effect transistors, a plurality of ink via, and a plurality of scribes.

17. The integrated circuit of claim 16, wherein the plurality of logic transistors are arranged in a plurality of orientations with respect to the sectional cuts and the plurality of power field-effect transistors are arranged in a plurality of orientations with respect to the sectional cuts.

18. The integrated circuit of claim 15, further comprising a plurality of structures arranged adjacent the plurality of devices wherein the sectional cuts through the integrated circuit completely reveals a plurality of characteristics of the plurality of structures, wherein the amount of the sectional cuts is substantially less than an amount of the revealed characteristics of the structures.

19. The integrated circuit of claim 15, wherein the plurality of device characteristics comprise at least one of a heater length, a heater width, a fuse length, a fuse width, a scribe step coverage, a transistor length, a transistor width, a contact size, a polycrystalline Silicon line width, a polycrystalline Silicon line space, an N-implant depth, a P-implant depth, a lightly-doped drain (“

LDD”

) implant depth, a LDD implant space, an NWELL depth, metal to implant contact width, a contact to polycrystalline Silicon space on an active region, a polycrystalline Silicon spacing, a polycrystalline Silicon line width, metal to metal spacing, metal to metal via, a metal line width, and a metal to metal to polycrystalline Silicon overlap.

20. The integrated circuit of claim 15, wherein at least one of the sectional cuts comprises a cross sectional cut.