Limiter circuit and semiconductor integrated circuit thereof

• US 20060139821A1
• Filed: 06/11/2004
• Published: 06/29/2006
• Est. Priority Date: 06/13/2003
• Status: Abandoned Application

• Current Assignee: Tadahiro Ohmi, Niigata Seimitsu Co., Ltd. (Tetsuo Funai)
• Original Assignee: Tadahiro Ohmi, Niigata Seimitsu Co., Ltd. (Tetsuo Funai)
• Inventors: Ohmi, Tadahiro, Sugawa, Shigetoshi, Teramoto, Akinobu, Miyagi, Hiroshi, Nishimuta, Takefumi
• Application Number:
  US10/560,646
• Publication Number:
  US 20060139821A1
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H03G 1/0023 in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 7/00 Volume compression or expansion in amplifiers frequency dependent H03G9/00
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30

Abstract

A rectangular parallelepiped p-channel MOS transistor 21 having a height of H_B and a width of W_B is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the p-channel MOS transistor 21. A source and a drain are formed on both sides of a gate electrode 26 to form a MOS transistor. A differential amplification circuit including MOS transistors 61 and 62 configures a limiter circuit. Thus, the gain of the limiter circuit can be designed large.

Claims

1. A limiter circuit formed on a semiconductor integrated circuit substrate, comprising:

a differential amplification circuit comprising an MIS field-effect transistor in which a projecting portion is formed by a silicon substrate having a first crystal surface as a primary surface and a second crystal surface as a side surface, terminated hydrogen on the silicon surface is removed in plasma atmosphere of an inert gas, then a gate insulating film is formed on at least a part of a top surface and the side surface of the projecting portion at a temperature at or lower than about 550°

C. in the plasma atmosphere, a gate is formed on the gate insulating film, and a drain and a source are formed on both sides enclosing the gate insulating film of the projecting portion.

2. The limiter circuit according to claim 1, wherein

a channel is formed on the first crystal surface of the top surface and the second crystal surface of the side surface of the projecting portion, and a channel width of the MIS field-effect transistor is at least a total of channel widths on the top surface and the side surface.

3. The limiter circuit according to claim 1, wherein

the projecting portion has the top surface comprising a silicon surface (100), a side surface comprising a silicon surface (110), and the source and drain are formed on the projecting portion enclosing the gate and in left and right areas of the projecting portion of the silicon substrate.

4. The limiter circuit according to claim 1, wherein

the limiter circuit comprises a p-channel MIS field-effect transistor and n-channel MIS field-effect transistor, and a gate width of a top surface and a side surface of a projecting portion of the p-channel MIS field-effect transistor is set such that current drive capability of the p-channel MIS field-effect transistor can be substantially equal to current drive capability of the n-channel MIS field-effect transistor.

5. The limiter circuit according to claim 1, wherein

the limiter circuit comprises first and second MIS field-effect transistors forming a differential amplification circuit for receiving an FM-modulated signal at a gate, and a third MIS field-effect transistor forming a constant current circuit commonly connected to a source or a drain of the first and second MIS field-effect transistors.

6. A semiconductor integrated circuit comprising on a same circuit substrate:

a circuit comprising a p-channel MIS field-effect transistor and an n-channel MIS field-effect transistor in which a projecting portion is formed by a silicon substrate having a first crystal surface as a primary surface and a second crystal surface as a side surface, terminated hydrogen on the silicon surface is removed in plasma atmosphere of an inert gas, then a gate insulating film is formed on at least one of the top surface and the side surface of the projecting portion at a temperature at or lower than about 550°

C. in the plasma atmosphere, a gate is formed on the gate insulating film, and a drain and a source are formed on both sides enclosing the gate insulating film of the projecting portion; and

a limiter circuit comprising a differential amplification circuit having the p-channel MIS field-effect transistor or the n-channel MIS field-effect transistor.

7. The semiconductor integrated circuit according to claim 6, wherein

gate widths of the top surface and the side surface of the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor are set such that the current drive capability of the p-channel MIS field-effect transistor can be substantially equal to current drive capability of the n-channel MIS field-effect transistor.

8. The semiconductor integrated circuit according to claim 6, wherein

the limiter circuit comprises a CMOS circuit having the p-channel MIS field-effect transistor and the n-channel MIS field-effect transistor.