Semiconductor device with mechanism for leak defect detection

• US 20060139822A1
• Filed: 03/22/2005
• Published: 06/29/2006
• Est. Priority Date: 12/24/2004
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Fujitsu Limited
• Inventors: Kurita, Yuji, Nishiwaki, Hitoaki, Yamashita, Hiroyoshi
• Granted Patent: US 7,471,099 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/20753 larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20754 larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor device includes a plurality of signal terminals, a first power supply terminal, a second power supply terminal, a core circuit coupled to the plurality of signal terminals and the first power supply terminal, a plurality of first transistors coupled between the respective signal terminals and the second power supply terminal, and a plurality of second transistors coupled between the respective signal terminals and a ground potential, wherein the core circuit is configured to make the first transistors conductive and nonconductive alternately and make the second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to the given signal terminal.

Claims

1. A semiconductor device, comprising:

a plurality of signal terminals;

a first power supply terminal;

a second power supply terminal;

a core circuit coupled to said plurality of signal terminals and said first power supply terminal;

a plurality of first transistors coupled between the respective signal terminals and said second power supply terminal; and

a plurality of second transistors coupled between the respective signal terminals and a ground potential,

wherein said core circuit is configured to make said first transistors conductive and nonconductive alternately and make said second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to said given signal terminal.

2. The semiconductor device as claimed in claim 1, wherein said plurality of signal terminals are operable to output signals from said core circuit to an exterior of said semiconductor device at a time of normal operation, and said core circuit is configured to set signal levels of said signals by controlling conductive/nonconductive states of said first transistors and said second transistors at the time of normal operation.

3. The semiconductor device as claimed in claim 1, further comprising a plurality of third transistors coupled between the respective signal terminals and a signal output power supply potential connected to said first power supply terminal, wherein said plurality of signal terminals are operable to output signals from said core circuit to an exterior of said semiconductor device at a time of normal operation, and said core circuit is configured to set signal levels of said signals by controlling conductive/nonconductive states of said third transistors and said second transistors at the time of normal operation.

4. The semiconductor device as claimed in claim 1, wherein said first transistors and said second transistors are fixedly placed in a nonconductive state at times other than the time of test operation, thereby to provide an ESD protection function.

5. The semiconductor device as claimed in claim 1, further comprising a circuit coupled between one or more control signal outputs of said core circuit and gate nodes of said first transistors and said second transistors to make said first transistors conductive and nonconductive alternately and make said second transistors nonconductive and conductive alternately in response to the one or more control signal outputs at the time of test operation.

6. The semiconductor device as claimed in claim 1, wherein said second power supply terminal is connected only to said first transistors.

7. A semiconductor device, comprising:

a first chip;

a second chip;

a package containing said first chip and said second chip, wherein said first chip includes;

a plurality of signal terminals connected to said second chip;

a first power supply terminal connected to an exterior of said package;

a second power supply terminal connected to an exterior of said package;

a core circuit coupled to said plurality of signal terminals and said first power supply terminal;

a plurality of first transistors coupled between the respective signal terminals and said second power supply terminal; and

a plurality of second transistors coupled between the respective signal terminals and a ground potential,

wherein said core circuit is configured to make said first transistors conductive and nonconductive alternately and make said second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to said given signal terminal.

8. The semiconductor device as claimed in claim 7, wherein said plurality of signal terminals are operable to output signals from said core circuit to said second chip at a time of normal operation, and said core circuit is configured to set signal levels of said signals by controlling conductive/nonconductive states of said first transistors and said second transistors at the time of normal operation.

9. The semiconductor device as claimed in claim 7, wherein said first chip further includes a plurality of third transistors coupled between the respective signal terminals and a signal output power supply potential, and wherein said plurality of signal terminals are operable to output signals from said core circuit to an exterior of said semiconductor device at a time of normal operation, and said core circuit is configured to set signal levels of said signals by controlling conductive/nonconductive states of said third transistors and said second transistors at the time of normal operation.

10. The semiconductor device as claimed in claim 7, wherein said signal terminals are not connected to an exterior of said package.