Non-volatile semiconductor storage device performing ROM read operation upon power-on

• US 20060139985A1
• Filed: 02/16/2006
• Published: 06/29/2006
• Est. Priority Date: 10/30/2002
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kanda, Kazushige, Nakamura, Hiroshi
• Granted Patent: US 7,196,950 B2
• Time in Patent Office: Days
• US Class Current: 365/94
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pads are connected to the delay circuit. Delay time in the delay time is controlled according to a chip address supplied to these two pads.

Claims

1-21. -21. (canceled)

22. A data read method for a semiconductor device having a plurality of independently-controllable ROM regions;

inputting a read command and a read address after a power supply voltage is applied, the read command and read address including information that corresponds to one of the ROM regions; and

reading data out of the ROM region specified by the information included in the read command and read address, after the read command and read address are input.

23. The method according to claim 22, wherein the independently- controllable ROM regions are 2n in number, and the semiconductor device includes n pads so as to specify the information corresponding to one of the ROM regions.

24. The method according to claim 22, wherein each of the ROM regions includes a delay circuit, and data is read out of the ROM region specified by the information included in the read command and read address, after the read command and read address are input and after lapse of a delay time provided by a delay circuit corresponding to the ROM region specified by the information included in the read command and read address.

25. The method according to claim 22, wherein a plurality of memory chips are provided, and

the ROM regions include:

a first ROM region which is included in a first memory chip of the memory chips; and

a second ROM region which is different from the first memory chip and included in a second memory chip of the memory chip.

26. The method according to claim 24, wherein a plurality of memory chips are provided, and

the ROM regions include:

a first ROM region which is included in a first memory chip of the memory chips; and

a second ROM region which is different from the first memory chip and included in a second memory chip of the memory chip.

27. The method according to claim 26, wherein the independently-controllable ROM regions are 2n in number, and the semiconductor device includes n pads so as to specify the information corresponding to one of the ROM regions.

28. The method according to claim 26, wherein a delay time provided by a delay circuit included in the first ROM region and a delay time provided by a delay circuit included in the second ROM region differ from each other.

29. The method according to claim 28, wherein each of the ROM regions includes an NAND flash memory.

30. The method according to claim 22, wherein each of the ROM regions include an NAND flash memory.