MAGNETIC MEMORY DEVICE AND METHOD

• US 20060139992A1
• Filed: 11/29/2005
• Published: 06/29/2006
• Est. Priority Date: 12/03/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hwang, In-jun, Kim, Tae-wan, Jeong, Won-cheol
• Granted Patent: US 7,508,699 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence

Abstract

An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction. Methods of operating and manufacturing these magnetic random access memories are also disclosed.

Claims

1. A magnetic random access memory device, comprising:

a magnetic tunnel junction including a free layer;

a first magnetic field generating component having a first portion that covers a surface of the free layer; and

an electric power source connected to the first magnetic field generating component via a connection that covers less than half of the first portion of the first magnetic field generating means.

2. The device of claim 1, wherein the connection covers a second portion of the first magnetic field generating component that does not cover the free layer.

3. The device of claim 2, wherein the connection covers only the second portion of the first magnetic field generating means.

4. The device of claim 1, wherein electric current that flows between the electric power source and the first magnetic field generating component also flows via the first portion in a direction parallel to a plane of the free layer surface covered by the first magnetic field generating means.

5. The device of claim 4, comprising a second electrode connected to the magnetic tunnel junction, wherein the magnetic tunnel junction is located between the first and second electrodes and the electric current also traverses the second electrode in a direction parallel to the plane of the free layer surface covered by the first magnetic field generating means.

6. The device of claim 1, wherein the electric power source comprises a bit line connected to the first magnetic field generating component and extending over the free layer.

7. The device of claim 1, wherein an area of the free layer surface is less than about 0.12 square microns.

8. The device of claim 1, comprising a digit line, wherein the magnetic tunnel junction is located between the first magnetic field generating component and the digit line.

9. The device of claim 8, wherein an area of the free layer surface is larger than about 0.3 square microns.

10. A magnetic random access memory device, comprising:

a magnetic tunnel junction;

first and second magnetic field generating component directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction;

an electric power source having one pole connected to the first magnetic field generating component via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second magnetic field generating component and the magnetic tunnel junction.

11. The device of claim 10, wherein electric current flowing between the first and second magnetic field generating component via the magnetic tunnel junction also traverses the first and second magnetic field generating component along the magnetic tunnel junction in directions that are substantially parallel to the magnetic tunnel junction.

12. The device of claim 11, wherein the magnetic tunnel junction comprises a free layer and wherein the electric power source comprises a bit line connected to the first magnetic field generating component and extending over the free layer.

13. The device of claim 12, wherein an area of the free layer surface facing the first magnetic field generating component is less than about 0.12 square microns.

14. The device of claim 12, comprising a digit line, wherein the second electrode and the magnetic tunnel junction are located between the first magnetic field generating component and the digit line.

15. The device of claim 14, wherein an area of the free layer surface facing the first magnetic field generating component is larger than about 0.3 square microns.

16. A method for controlling a magnetic random access memory device comprising a magnetic tunnel junction and first and second magnetic field generating component directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, the method comprising:

switching the device via a first electric current traversing the first and second magnetic field generating component in directions substantially parallel to direct connections between the first and second magnetic field generating component and the magnetic tunnel junction.

17. The method of claim 16, comprising:

reading a state of the magnetic random access memory device via a voltage applied across the first and second magnetic field generating means, wherein a corresponding electric current through the magnetic tunnel junction is less than the first electric current.

18. The method of claim 16, wherein the magnetic random access memory device comprises a digit line and the second magnetic field generating component and the magnetic tunnel junction are located between the first magnetic field generating component and the digit line, the switching comprising:

applying a second electric current to the digit line, simultaneous with the first electric current.

19. A method of manufacturing a magnetic memory device, the method comprising:

forming a transistor in a substrate;

forming on the substrate a first interlayer insulating layer covering the transistor;

forming in the first interlayer insulating layer a via hole exposing a source of the transistor;

filling the via hole with a conductive plug;

forming on the first interlayer insulating layer a first magnetic field generating component contacting the conductive plug; and

forming an MTJ (magnetic tunnel junction) on a predetermined region of the first magnetic field generating component separated from the conductive plug.

20. The method of claim 19, wherein the first magnetic field generating component is a lower electrode pad layer connecting the conductive plug and the MTJ.

21. The method of claim 20, wherein the width and the thickness of the lower electrode pad layer are 100 nm or less.

22. The method of claim 19, wherein the forming of the first interlayer insulating layer comprises:

forming on the substrate a first insulating layer covering the transistor;

forming on the first insulating layer a second magnetic field generating component perpendicular to the first magnetic field generating component; and

forming on the first insulating layer a second insulating layer covering the second magnetic field generating component.

23. The method of claim 22, wherein the second magnetic field generating component is a conductive wire generating a magnetic field in the direction of a hard axis of the MTJ.

24. The method of claim 19, further comprising:

forming on the first interlayer insulating layer a second interlayer insulating layer covering the first magnetic generating component and the MTJ;

forming in the second interlayer insulating layer a via hole exposing a top surface of the MTJ; and

forming on the second interlayer insulating layer a bit line filling the via hole.

25. The method of claim 24, wherein the MTJ and the bit line are separated by at least 300 nm.

26. The method of claim 19, further comprising:

forming on the first interlayer insulating layer a second interlayer insulating layer covering the first magnetic field generating component and the MTJ;

planarizing the second interlayer insulating layer until a top surface of the MTJ is exposed;

forming on the second interlayer insulating layer a second magnetic field generating component having a first end portion contacting the exposed top surface of the MTJ;

forming on the second interlayer insulating layer a third interlayer insulating layer covering the second magnetic field generating component;

forming in the third interlayer insulating layer a via hole exposing a second end portion of the second magnetic field generating component; and

forming on the third interlayer insulating layer a bit line filing the via hole exposing the second magnetic field generating component.

27. The method of claim 26, wherein the first and second magnetic field generating components are perpendicular to each other.

28. The method of claim 26, wherein the second magnetic field generating component and the bit line are separated by about 300 nm.

29. The method of claim 26, wherein the second magnetic field generating component is an upper electrode pad layer connecting the bit line and the top surface of the MTJ.

30. The method of claim 29, wherein the width and the thickness of the upper electrode pad layer are 100 nm or less.

31. The method of claim 19, wherein the transistor comprises first and second transistors which share one drain, the via hole comprises first and second via holes respectively exposing sources of the first and second transistors, the conductive plug comprises first and second conductive plugs respectively filling the first and second via holes, the first magnetic field generating component comprises a first lower electrode pad layer having a first end portion contacting the first conductive plug and a second lower electrode pad layer having a first end portion contacting the second conductive plug, and the MTJ comprises a first MTJ formed on a second end portion of the first lower electrode pad layer and a second MTJ formed on a second end portion of the second lower electrode pad layer.

32. The method of claim 26, wherein the transistor comprises first and second transistors which share one drain, the via hole comprises first and second via holes respectively exposing sources of the first and second transistors, the conductive plug comprises first and second conductive plugs respectively filling the first and second via holes, the first magnetic field generating component comprises a first lower electrode pad layer having a first end portion contacting the first conductive plug and a second lower electrode pad layer having a first end portion contacting the second conductive plug, the MTJ comprises a first MTJ formed on a second end portion of the first lower electrode pad layer and a second MTJ formed on a second end portion of the second lower electrode pad layer;

and the second magnetic field generating component comprises a first upper electrode pad layer having a first end portion contacting a top surface of the first MTJ and a second end portion contacting the bit line and a second upper electrode pad layer having a first end portion contacting a top surface of the second MTJ and a second end portion contacting the bit line.

33. The method of claim 32, wherein the first and second lower electrode pad layers and the first and second upper electrode pad layers have the same thickness and the same width.

34. A method of manufacturing a magnetic memory device, the method comprising:

forming a transistor in a substrate;

forming on the substrate a first interlayer insulating layer covering the transistor;

forming in the first interlayer insulating layer a via hole exposing a source of the transistor;

filling the via hole with a conductive plug;

forming on the first interlayer insulating layer an MTJ (magnetic tunnel junction) cell covering a top surface of the conductive plug;

forming on the first interlayer insulating layer a second interlayer insulating layer surrounding sides of the MTJ; and

forming on the second interlayer insulating layer a first magnetic field generating component having a first end portion contacting a top surface of the MTJ and a second end portion contacting the bit line.

35. The method of claim 34, wherein the first magnetic field generating component is an upper electrode pad layer.

36. The method of claim 35, wherein the thickness and the width of the upper electrode pad layer are 100 nm or less.