Flash memory device

• US 20060139997A1
• Filed: 12/09/2005
• Published: 06/29/2006
• Est. Priority Date: 12/27/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Park, Hee Sik, Park, Byung Soo, Lee, Kyeong Bock
• Granted Patent: US 7,310,280 B2
• Time in Patent Office: Days
• US Class Current: 365/185.200
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A flash memory device comprises a first group of dummy memory cells disposed between source selection transistors, which are coupled to a source selection line, and memory cells coupled to a first wordline. The flash memory device further comprises a second group of dummy memory cells disposed between drain selection transistors, which are coupled to a drain selection line, and memory cells coupled to the last wordline. The flash memory device is configured to prevent program disturbance in deselected cell strings and degradation of programming/erasing speeds in a selected cell string.

Claims

1. A flash memory device comprising:

a first selection transistor coupled to a bitline;

a second selection transistor coupled to a common source line;

a plurality of memory cells coupled between the first and second selection transistors, each memory cell being coupled to a wordline, and

a dummy memory cell provided between one of the memory cells and the second selection transistor.

2. The flash memory device of claim 1, wherein the dummy memory cell is provided adjacent to the second selection transistor.

3. The flash memory device of claim 1, wherein the device comprises a plurality of first selection transistors, a plurality of second selection transistors, a plurality of memory cell arrays, and a plurality of dummy memory cells, each memory cell array provided between one of the first selection transistors and one of the second selection transistors, at least one dummy memory cell provided between each of the memory cell arrays and each of the second selection transistors.

4. The flash memory device of claim 3, wherein the plurality of dummy memory cells includes first dummy memory cells, each of the first dummy memory cells being provided between a first memory cell and the corresponding second selection transistor, the first memory cell being coupled to a first wordline and being most proximate to the corresponding second selection transistor amongst the memory cells in the same memory cell array,

wherein the first memory cells coupled to the first wordline and a deselected bitline of the bitlines are substantially free from an effect of program disturbance.

5. The flash memory as set forth in claim 1, wherein the dummy memory cells comprise dummy transistors.

6. The flash memory as set forth in claim 5, wherein a dummy wordline coupled to the dummy transistors is supplied with a power source voltage during program and read operations, and supplied with a ground voltage during an erase operation.

7. The flash memory as set forth in claim 4, wherein a dummy wordline coupled to the dummy memory cells is supplied with a voltage that is more than twice a power source voltage and less than a program inhibit voltage applied to the wordlines.

8. The flash memory as set forth in claim 4, wherein a dummy wordline coupled to the dummy memory cells is supplied with a program inhibit voltage applied to the plurality of wordlines during a program operation.

9. The flash memory as set forth in claim 4, wherein a dummy wordline coupled to the dummy memory cells is supplied with a ground voltage during an erase operation and supplied with a read voltage applied to the wordlines during a read operation.

10. The flash memory as set forth in claim 1, wherein the dummy memory cell has the same size as the plurality of memory cells coupled between the first and second selection transistors.

11. The flash memory as set forth in claim 1, wherein each the memory cells are configured to store at least two bits of data, the dummy memory cell not being configured to store at least two bits of data.

12. A flash memory device comprising:

first selection transistors each coupled to a plurality of bitlines;

second selection transistors coupled to a common source line; and

a plurality of memory cell arrays provided between the first and second selection transistors, each memory cell array provided between each first selection transistor and each second selection transistor; and

a plurality of wordlines, each wordline being coupled to a plurality of memory cells in different memory cell arrays,

wherein each memory cell array includes at least one dummy memory cell.

13. The flash memory as set forth in claim 12, wherein the at least one dummy memory cell in each memory cell array is provided between a last memory cell of the each memory cell array and the first selection transistor, the last memory cell being most proximate to the first selection transistor of the each memory cell array and being coupled to a last wordline, and

wherein threshold voltages of memory cells coupled to the last wordline and a selected bitline of the plurality of bitlines are equal to threshold voltages of the other memory cells.

14. The flash memory as set forth in claim 12, wherein a dummy wordline coupled to the dummy memory cells is supplied with a program inhibit voltage applied to the plurality of wordlines during a program operation.

15. The flash memory as set forth in claim 12, wherein a dummy wordline coupled to the dummy transistors is supplied with a ground voltage during an erase operation, and supplied with a read voltage applied to the plurality of wordlines during a read operation.

16. The flash memory as set forth in claim 12, wherein the memory cells including the dummy cells have substantially the same size.

17. The flash memory as set forth in claim 12, wherein each of the memory cells except the dummy memory cells are configured to store at least two bits of data.

18. A flash memory device comprising:

first selection transistors each coupled to a plurality of bitlines;

second selection transistors coupled to a common source line; and

a plurality of memory cells coupled between the first and second selection transistors and coupled to a plurality of wordlines,

wherein the plurality of memory cells include a first group of dummy memory cells coupled between memory cells coupled to a first wordline and the second selection transistors, and the plurality of memory cells further include a second group of dummy memory cells coupled between memory cells coupled to a last wordline and the first selection transistors.

19. The flash memory as set forth in claim 18, wherein memory cells coupled to the first and last wordlines, and a deselected bitline of the plurality of bitlines do not exhibit a significant program disturbance effect.

20. The flash memory as set forth in claim 18, wherein threshold voltages of memory cells coupled to the first and last wordlines and a selected bitline of the plurality of bitlines are equal to threshold voltages of the other memory cells coupled between the first and second selection transistors.

21. The flash memory as set forth in claim 18, wherein the first and second group of dummy memory cells comprise dummy transistors.

22. The flash memory as set forth in claim 21, wherein a first dummy wordline coupled to the first group of dummy transistors and a second dummy wordline coupled to the second group of dummy transistors are supplied with a power source voltage during program and read operations, and supplied with a ground voltage during an erase operation.

23. The flash memory as set forth in claim 18, wherein a first dummy wordline coupled to the first group of dummy transistors and a second dummy wordline coupled to the second group of dummy transistors are supplied with a voltage higher than twice a power source voltage and lower than a program inhibit voltage applied to the plurality of wordlines during a program operation.

24. The flash memory as set forth in claim 18, wherein a first dummy wordline coupled to the first group of dummy transistors and a second dummy wordline coupled to the second group of dummy transistors are supplied with a program inhibit voltage applied to the plurality of wordlines during a program operation.

25. The flash memory as set forth in claim 18, wherein a first dummy wordline coupled to the first group of dummy transistors and a second dummy wordline coupled to the second group of dummy transistors are supplied with a ground voltage during an erase operation and supplied with a read voltage applied to the plurality of wordlines during a read operation, and wherein the first and second group of dummy memory cells have the same size as the plurality of memory cells coupled between the first and second selection transistors.

26. The flash memory as set forth in claim 18, wherein the memory cells except the first and second group of dummy memory cells are configured to stored at least two bits of data.