Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information

• US 20060140026A1
• Filed: 12/28/2004
• Published: 06/29/2006
• Est. Priority Date: 12/28/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Bosch, Derek J., Ilkbahar, Alper
• Granted Patent: US 7,277,336 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A method is provided comprising reading a set of memory cells indicating whether stored redundancy information is reliable and, if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information. Another method is provided comprising reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells; if the set of memory cells indicates that data can be reliably stored in the group of memory cells, storing data in the group of memory cells; and if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells, storing data in a group of memory cells in a redundant memory. In another preferred embodiment, a method for providing memory redundancy is provided.

Claims

1. A method for reading memory, the method comprising:

(a) reading a set of memory cells indicating whether stored redundancy information is reliable; and

(b) if the set of memory cells indicates that the stored redundancy information is reliable, determining whether to read primary memory or redundant memory based on the stored redundancy information.

2. The method of claim 1 further comprising:

(c) if the set of memory cells does not indicate that the stored redundancy information is reliable, reading an address of the redundant memory identified by a direct mapping operation from an address associated with the set of memory cells.

3. The method of claim 1, wherein the redundancy information comprises a first field for storing an indication of whether the redundant memory was written to, a second field for storing an indication of whether a write operation to the redundant memory was successful, and a third field for storing an address in the redundant memory.

4. The method of claim 3, wherein (b) comprises reading the primary memory if the first field does not store an indication that the redundancy memory was written to.

5. The method of claim 3, wherein (b) comprises reading the redundant memory at the address stored in the third field if the first field stores an indication that the redundant memory was written to and the second field stores an indication that a write operation to the redundant memory was successful.

6. The method of claim 3, wherein (b) comprises generating an error if the first field stores an indication that the redundant memory was written to and the second field does not store an indication that a write operation to the redundant memory was successful.

7. The method of claim 1, wherein the set of memory cells indicates that the stored redundancy information is reliable when the set of memory cells is in a programmed state.

8. The method of claim 1, wherein the redundancy information comprises row redundancy information.

9. The method of claim 1, wherein the redundancy information comprises column redundancy information.

10. The method of claim 1, wherein the memory cells are part of a three-dimensional memory array comprising a plurality of layers of memory cells vertically stacked over a silicon substrate.

11. A method for writing to memory, the method comprising:

(a) reading a set of memory cells associated with a group of memory cells in a primary memory, the set of memory cells indicating whether data can be reliably stored in the group of memory cells in the primary memory;

(b) if the set of memory cells indicates that data can be reliably stored in the group of memory cells in the primary memory, storing data in the group of memory cells in the primary memory; and

(c) if the set of memory cells does not indicate that data can be reliably stored in the group of memory cells in the primary memory, storing data in a redundant memory.

12. The method of claim 11, wherein (c) comprises storing data at an address of redundant memory identified by a direct mapping operation from an address associated with the set of memory cells.

13. The method of claim 11 further comprising storing redundancy information comprising a first field for storing an indication of whether the redundant memory was written to, a second field for storing an indication of whether a write operation to the redundant memory was successful, and a third field for storing an address in the redundant memory.

14. The method of claim 13 further comprising:

if there is an error in storing the data in (b) or (c), storing the data at a first address in the redundant memory.

15. The method of claim 14, if the data is successfully stored in the first address in the redundant memory, storing an indication of that the redundant memory was written to in the first field, storing an indication that the write operation to the redundant memory was successful in the second field, and storing the first address in the third field.

16. The method of claim 14, if there is an error in storing the data in at the first address in the redundant memory, generating an error.

17. The method of claim 11, wherein the memory cells are part of a three-dimensional memory array comprising a plurality of layers of memory cells vertically stacked over a silicon substrate.

18. The method of claim 11 further comprising, during sort flow of a memory array comprising the set of memory cells, attempting to program the set of memory cells.

19. The method of claim 11 further comprising, in the field, attempting to program the set of memory cells.

20. A method for providing memory redundancy in a memory device, the method comprising:

(a) attempting to program a set of memory cells in a redundant memory area;

(b) attempting to program a set of memory cells in a main memory area associated with the redundant memory area; and

(c) if the set of memory cells in the main memory area are not programmed successfully;

(c1) determining whether the set of memory cells in the redundant area were programmed successfully; and

(c2) if the set of memory cells in the redundant area were programmed successfully, allocate the redundant area for the main memory area.

21. The method of claim 20 further comprising:

(c3) if the set of memory cells in the redundant area were not programmed successfully, discarding the memory device.

22. The method of claim 20, wherein the redundant memory area is directly mapped to the main memory area.

23. The method of claim 20, wherein (c) further comprises determining whether the redundant area was previously allocated to another main memory area, and wherein (c2) is performed if the redundant area was not previously allocated to another main memory area.

24. The method of claim 20, wherein (a)-(c2) are performed during sort flow of the memory device.

25. The method of claim 20, wherein the redundant memory area and the main memory area comprise respective rows.

26. The method of claim 20, wherein the redundant memory area and the main memory area comprises a plurality of memory cells vertically stacked over a silicon substrate.