Pulse width modulation amplifier

• US 20060140090A1
• Filed: 12/23/2005
• Published: 06/29/2006
• Est. Priority Date: 12/28/2004
• Status: Active Grant

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Morishima, Morito
• Granted Patent: US 7,656,946 B2
• Time in Patent Office: Days
• US Class Current: 369/47.520
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers

Abstract

The invention provides a pulse width modulation amplifier that includes a correction circuit, an envelope detector, a level detector, a PWM carrier generator, an interpolation arithmetic circuit, and a PWM circuit. The envelope detector detects an envelope of digital data to be input. The correction circuit performs distortion correction, frequency characteristic correction, and ΔΣ correction, for the input digital data. The level detector detects levels of the digital data supplied by the envelope detector. The PWM carrier generator gates a carrier signal having a frequency corresponding to the output of the level detector. The interpolation arithmetic circuit generates interpolation data synchronous with the carrier signal from the digital data. The PWM circuit converts the interpolation data into a pulse width modulation signal based on the carrier signal.

Claims

1. A pulse width modulation amplifier comprising:

a level detector for detecting a level of digital data to be input;

a carrier generator for generating a carrier signal successively increases a frequency corresponding to a detection result by the level detector; and

a converter for converting the digital data to a pulse width modulation signal based on the carrier signal.

6. A pulse width modulation amplifier as recited in one of claims 1-5, further comprising:

a clock generator for generating a differential clock synchronous with the carrier signal;

a latch for reading in an output of the converter based on the differential clock and outputting a differential signal;

an amplifier for amplifying the differential signal from the latch and outputting the amplified differential signal; and

a differential driver driven by the amplified differential signal from the amplifier.

2. A pulse width modulation amplifier comprising:

an envelope detector for detecting an envelope of digital data to be input;

a level detector for detecting a level of the digital data from an out put of the envelope detector;

a carrier generator for generating a carrier signal that successively increases a frequency corresponding to a detection result by the level detector;

an interpolation data generator for generating interpolated data synchronous with the carrier signal from the digital data; and

a converter for converting the interpolated data to a pulse width modulation signal based on the carrier signal.

3. A pulse width modulation amplifier comprising:

a level detector for detecting a level of digital data to be put and outputting a detection signal when the level of the digital data becomes smaller than a predetermined value and remains smaller for a predetermined time;

a carrier generator for generating a carrier signal that increases successively synchronous with an input timing of to digital data and, to carrier signal successively increasing having a frequency higher than the input timing when the detection signal from the level detector is received;

an interpolation data generator for generating interpolation data synchronous with the carrier signal from the digital data; and

a converter for converting the digital data to a pulse width modulation signal based on the carrier signal.

4. A pulse width modulation amplifier as recited in claim 3, wherein the carrier generator generates twice as large a carrier frequency as the input pulse when the detection signal from the level detector is received.

5. A pulse width modulation amplifier comprising:

a level detector for detecting a level of digital data to be input;

a carrier generator for generating a carrier signal that increases successively synchronous with an input timing of the digital data; and

a converter for converting the digital data to a pulse width modulation signal based on the carrier signal, and for outputting a duty and a frequency fixed signal, when a detection result by the level detector is zero data, direct current data, or a small amount of data and the data is continuous.

7. A pulse width modulation amplifier comprising:

an absolute value output circuit for outputting an absolute value of digital data to be input;

a period data output circuit for outputting period data corresponding to the absolute value from the absolute value output circuit;

a carrier generator for generating a carrier signal that successively increases a frequency corresponding to the period data; and

a converter for converting the digital data to a pulse width modulation signal based on the carrier signal.

8. A pulse width modulation amplifier as recited in claim 7, wherein the converter decides a pulse width y of the pulse width modulation signal based on the following equation

y/(H+Xabs)=(H±

Xabs)/2H,

where H is a maximum value of the digital data, and Xabs is an absolute value of the digital data.