Self-healing link sequence counts within a circular buffer

• US 20060140188A1
• Filed: 12/28/2004
• Published: 06/29/2006
• Est. Priority Date: 12/28/2004
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shearer, Robert A., Wigglesworth, Craig A., Voytovich, Martha E.
• Granted Patent: US 7,499,452 B2
• Time in Patent Office: Days
• US Class Current: 370/394
• CPC Class Codes: G06F 13/4208 being a system bus, e.g. VME bus, Futurebus, Multibus
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9031 Wraparound memory, e.g. overrun or underrun detection
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

Methods and apparatus that allow recovery in the event that sequence counts used on receive and transmit sides of a communications link become out of sync are provided. In response to receiving a packet with an expected sequence count from a receiving device, a transmitting device may adjust pointers into a transmit buffer allowing the transmitting device to begin transmitting packets with the sequence count expected by the receiving device.

Claims

1. A method of communicating with an external device over a bus utilizing one or more virtual channels, at least one of the virtual channels utilizing a transmit buffer to hold commands and data to be sent in packets to the external device, comprising:

maintaining a current sequence count for packets to be transmitted to the external device;

receiving a packet from the external device indicating an expected sequence count that does not match the current sequence count; and

adjusting the current sequence count to match the expected sequence count by modifying one or more pointers into the transmit buffer.

2. The method of claim 1, wherein adjusting the current sequence count to match the expected sequence count by modifying one or more pointers into the transmit buffer comprises:

setting a first pointer indicating an earliest packet in the transmit buffer that has been sent, but not acknowledged, to the same value as the expected sequence count.

3. The method of claim 2, wherein adjusting the current sequence count to match the expected sequence count by modifying one or more pointers into the transmit buffer further comprises:

adjusting a second pointer indicative of a location in the transmit buffer containing an earliest packet that has been transmitted but not yet cleared from the transmit buffer.

4. The method of claim 3, wherein adjusting the current sequence count to match the expected sequence count by modifying one or more pointers into the transmit buffer further comprises:

once the second pointer has reached a third pointer indicative of a next packet to be sent, adjusting the second and third pointers together.

5. The method of claim 4, wherein adjusting the current sequence count to match the expected sequence count by modifying one or more pointers into the transmit buffer further comprises:

once the second and third pointers have reached a fourth pointer indicative of the next entry in the transmit buffer to be written to, adjusting the second, third and fourth pointers to match the first pointer; and

subsequently, transmitting a packet having the expected sequence count to the external device.

6. The method of claim 1, wherein receiving a packet from the external device indicating an expected sequence count that does not match the current sequence count comprises receiving a periodically transmitted acknowledgement packet.

7. The method of claim 1, wherein the expected sequence count does also not match the sequence count of one or more previously sent and unacknowledged packets.

8. The method of claim 1, wherein maintaining a current sequence count comprises incrementing a pointer into the transmit buffer upon sending a packet to the external device.

9. An integrated circuit (IC) device, comprising:

one or more processor cores;

a bus interface for transferring data to and from an external device via an external bus;

a transmit buffer for holding packets of data to be sent from the one or more processor cores to the external device over the external bus; and

self-healing link logic circuitry configured to receive, from an external device, a packet containing an expected sequence count for packets transmitted to the external device by the IC device and, if a current sequence count maintained by the IC device does not match the expected sequence count, adjust the current sequence count to match the expected sequence count by modifying one or more pointers into the transmit buffer.

10. The device of claim 9, wherein the transmit buffer is a circular first-in first-out (FIFO) buffer.

11. The device of claim 9, wherein the self-healing link logic circuitry is configured to set a first pointer indicating an earliest packet in the transmit buffer that has been sent, but not acknowledged, to the same value as the expected sequence count.

12. The device of claim 11, wherein the self-healing link logic circuitry is configured to adjust a second pointer indicative of a location in the transmit buffer containing an earliest packet that has been transmitted but not yet cleared from the transmit buffer.

13. The device of claim 12, wherein the self-healing link logic circuitry is configured to, once the second pointer has reached a third pointer indicative of a next packet to be sent, adjust the second and third pointers together.

14. The device of claim 13, wherein:

the self-healing link logic circuitry is configured to, once the second and third pointers have reached a fourth pointer indicative of the next entry in the transmit buffer to be written to, adjusting the second, third and fourth pointers to match the first pointer; and

the device is thereby configured to subsequently transmit a packet having the expected sequence count to the external device.

15. A system, comprising:

at least one bus;

one or more external devices; and

a system on a chip (SOC) having one or more processor cores, a transmit buffer for holding packets of data to be sent from the one or more processor cores to the external device over the bus, and self-healing link logic circuitry configured to receive, from an external device, a packet containing an expected sequence count for packets transmitted to the external device by the SOC and, if a current sequence count maintained by the SOC does not match the expected sequence count, adjust the current sequence count to match the expected sequence count by modifying one or more pointers into the transmit buffer.

16. The system of claim 15, wherein the SOC transmit buffer is a circular first-in first-out (FIFO) buffer.

17. The system of claim 15, wherein the self-healing link logic circuitry is configured to set a first pointer indicating an earliest packet in the transmit buffer that has been sent, but not acknowledged, to the same value as the expected sequence count.

18. The system of claim 17, wherein the self-healing link logic circuitry is configured to adjust a second pointer indicative of a location in the transmit buffer containing an earliest packet that has been transmitted but not yet cleared from the transmit buffer.

19. The system of claim 18, wherein the self-healing link logic circuitry is configured to, once the second pointer has reached a third pointer indicative of a next packet to be sent, adjust the second and third pointers together.

20. The system of claim 15, wherein the one or more external devices comprises a graphics processing unit (GPU) and a memory controller.

21. The system of claim 20, wherein the memory controller is integrated with the GPU.

22. The system of claim 20, wherein the system is a gaming system and the virtual channels are used to send data packets containing graphical data from the SOC to the GPU.

23. The system of claim 20, wherein GPU comprises:

a transmit buffer for holding packets of data to be sent to the SOC over the bus; and

self-healing link logic circuitry configured to receive, from the SOC, a packet containing an expected sequence count for packets transmitted to the SOC by the SOC and, if a current sequence count maintained by the GPU does not match the expected sequence count, adjust the current sequence count maintained by the GPU to match the expected sequence count received from the SOC by modifying one or more pointers into the GPU transmit buffer.