Method and apparatus for storing bitplanes of coefficients in a reduced size memory

• US 20060140491A1
• Filed: 02/27/2006
• Published: 06/29/2006
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Edward L. Schwartz
• Original Assignee: Edward L. Schwartz
• Inventors: Schwartz, Edward L.
• Granted Patent: US 7,397,963 B2
• Time in Patent Office: Days
• US Class Current: 382/232
• CPC Class Codes: H04N 19/10 using adaptive coding
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/593 involving spatial prediction techniques
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/63 using sub-band based transform, e.g. wavelets
• CPC Class Codes: H04N 19/635 characterised by filter definition or implementation details
• CPC Class Codes: H04N 19/64 characterised by ordering of coefficients or of bits for transmission
• CPC Class Codes: H04N 19/647 using significance based coding, e.g. Embedded Zerotrees of Wavelets [EZW] or Set Partitioning in Hierarchical Trees [SPIHT]
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards

Abstract

A method and apparatus for storing bitplanes of coefficients in a reduced size memory is disclosed. In one embodiment, a method for encoding coefficients comprises applying one or more wavelet transforms to generate multiple coefficients and storing N bitplanes of each of the multiple coefficients in a first memory having multiple rows. Each of the multiple coefficients has a bit length greater than N bits, and each storage location in each of the rows stores a bit of either a more significant bitplane of the coefficients or a less significant bitplane of the coefficients. The storing of N bitplanes includes storing an indication for each row of the rows to indicate a location in each row at which bits of more significant bitplanes have started to be stored and after which bits of the multiple coefficients of the less significant bitplanes are no longer stored.

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43. A method comprising:

storing less than all bit planes of each of the plurality of coefficients in a first memory;

associating an indication with each of the coefficients, the indication indicating where the more significant bitplanes and less significant bit planes are stored for each coefficient.

44. The method defined in claim 43 wherein storage for each coefficient has a plurality of bits and stores a bit of either a more significant bitplane of the plurality of coefficients or a less significant bitplane of the plurality of coefficients.

45. The method defined in claim 43 wherein storing of the plurality of coefficients occurs prior to identification of the number of zero bit planes in the plurality of coefficients.

46. The method defined in claim 43 further comprising truncating bitplanes of the plurality of coefficients that are below the N bitplanes.

47. The method defined in claim 43 wherein the indication comprises a count.

48. The method defined in claim 47 further comprising:

counting zero bits in each of the more significant bit planes of the plurality of coefficients using a plurality of counters, wherein individual counters are associated with only one of the plurality of rows; and

stopping each counter of the plurality of counters associated with one of the most significant bitplanes when a one bit occurs in the one most significant bitplane of a coefficient.

49. The method defined in claim 43 wherein the indication for each row indicates a starting address at which bits of an associated more significant bitplane of the plurality of coefficients are stored.

50. The method defined in claim 43 further comprising a context model accessing coefficients stored in the first memory.

51. The method defined in claim 50 further comprising:

the context model generating an address to access a bit in the first memory; and

comparing the address with a counter value for the bitplane associated with the bit to determine if the bit is data that is not to be used by the context model.

52. The method defined in claim 43 wherein the plurality of coefficients comprises coefficients in other than an LL subband.

53. The method defined in claim 43 wherein the one or more wavelet transforms comprises a 5,3 transform.

54. The method defined in claim 43 further comprising storing the indication in a second memory different than the first memory.

55. An apparatus for encoding coefficients comprising:

means for applying one or more wavelet transforms to generate a plurality of coefficients;

means for storing N bitplanes of each of the plurality of coefficients in a first memory having a plurality of rows, where each of the plurality of coefficients has a bit length greater than N bits, and wherein each storage location in each of the plurality of rows stores a bit of either a more significant bitplane of the plurality of coefficients or a less significant bitplane of the plurality of coefficients, wherein storing N bitplanes includes

means for storing an indication for each row of the plurality of rows to indicate a location in said each row at which bits of more significant bitplanes have started to be stored and after which bits of the plurality of coefficients of the less significant bitplanes are no longer stored.