Method for fabricating semiconductor device

• US 20060141691A1
• Filed: 11/21/2005
• Published: 06/29/2006
• Est. Priority Date: 12/28/2004
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Jung-Nam
• Application Number:
  US11/284,565
• Publication Number:
  US 20060141691A1
• Time in Patent Office: Days
• US Class Current: 438/199
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A method for fabricating a semiconductor memory device is provided. The method includes: forming a trench in a portion of a substrate, defined as a cell region; forming a first polysilicon layer doped with N-type impurities on regions where N-type metal-oxide-semiconductor (MOS) transistors are to be formed in the cell region and the periphery region; forming a second polysilicon layer doped with P-type impurities on an area where a P-type MOS transistor is to be formed; forming a gate metal layer over the first and the second polysilicon layers; forming a gate hard mask layer on the gate metal layer; and patterning the gate hard mask layer, the gate metal layer, and the first and the second polysilicon layers to form gate patterns for the N-type MOS transistors in the cell region and the periphery region, and the P-type MOS transistor in the periphery region.

Claims

1. A method for fabricating a semiconductor memory device, comprising:

forming a trench in a portion of a substrate, defined as a cell region;

forming a gate oxide layer over the substrate including the trench;

forming a first polysilicon layer doped with N-type impurities on regions where N-type metal-oxide-semiconductor (MOS) transistors are to be formed in the cell region and the periphery region such that the first polysilicon layer fills the trench;

forming a second polysilicon layer doped with P-type impurities on an area where a P-type MOS transistor is to be formed;

forming a gate metal layer over the first polysilicon layer and the second polysilicon layer;

forming a gate hard mask layer on the gate metal layer; and

patterning the gate hard mask layer, the gate metal layer, and the first and the second polysilicon layers to form gate patterns for the N-type MOS transistors in the cell region and the periphery region, and the P-type MOS transistor in the periphery region.

2. The method of claim 1, wherein the forming of the second polysilicon layer includes:

forming the second polysilicon layer over the first polysilicon layer and the substrate; and

planarizing the second polysilicon layer by removing the second polysilicon layer formed over the first polysilicon layer, so that the first polysilicon layer remains in the cell region and the periphery region whereon the N-type MOS transistors are to be formed, and the second polysilicon layer remains in the periphery region whereon the P-type MOS transistor is to be formed.

3. The method of claim 2, wherein the N-type impurities include one of arsenic (As) and phosphorus (P).

4. The method of claim 2, wherein the first polysilicon layer is formed in a thickness ranging from approximately 500 Å

to approximately 1,000 Å

at a temperature ranging from approximately 500°

C. to approximately 600°

C. by utilizing one gas selected from phosphine (PH₃) and arsine (AsH₃), silane (SiH₄) gas and nitrogen (N₂) gas at an approximate ratio of 8-12;

1-3;

1-3.

5. The method of claim 2, wherein the P-type impurities include one of boron (B) and boron difluoride (BF₂).

6. The method of claim 2, wherein the second polysilicon layer is formed in a thickness ranging from approximately 500 Å

to approximately 1,000 Å

at a temperature ranging from approximately 500°

C. to approximately 600°

C. by utilizing boron trifluoride (BF₃) gas, silane (SiH₄) gas and nitrogen (N₂) gas at an approximate ratio of 8-12;

1-3;

1-3.

7. The method of claim 2, wherein the gate metal layer is formed by employing tungsten silicide.

8. The method of claim 2, wherein the gate metal layer is formed in a thickness ranging from approximately 500 Å

to approximately 1,500 Å

utilizing tungsten hexafluoride (WF₆) and SiH₄ gases.

9. The method of claim 2, wherein the gate hard mask layer is formed by employing nitride-based silicon.

10. The method of claim 2, wherein the gate hard mask layer is formed in a thickness ranging from approximately 2,000 Å

to approximately 2,500 Å

at a temperature ranging from approximately 600°

C. to approximately 800°

C. utilizing N₂, ammonia (NH₃) and dichlorosilane (SiH₂Cl₂) gases.