Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
First Claim
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1. A method of forming a transistor, comprising:
- forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween; and
wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer.
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Abstract
Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure'"'"'s channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.
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Citations
26 Claims
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1. A method of forming a transistor, comprising:
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forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween; and
wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer. - View Dependent Claims (2, 3)
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4. A method of forming a transistor, comprising:
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forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween, wherein forming each source/drain region includes;
forming a doped material structure against the wall of the trench;
diffusing dopants from the doped material structure into the wall of the trench;
removing the doped material structure from the trench; and
wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer. - View Dependent Claims (5, 6, 7, 8, 9)
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10. A method of forming a transistor, comprising:
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forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween, wherein forming each source/drain region includes;
ion implanting dopants into the wafer surface prior to forming the trench to form doped regions of a first type within a surface wafer material of a second type;
forming the trench between ion implanted regions after formation of the doped regions; and
wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer. - View Dependent Claims (11, 12, 13, 14)
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15. A method of forming a transistor, comprising:
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forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween, wherein forming each source/drain region includes angled ion implanting dopants into the trench wall to form doped regions of a first type within a wall material of a second type; and
wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer. - View Dependent Claims (16, 17, 18, 19)
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20. A method of forming a memory device, comprising:
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forming a number of memory cells, each cell including at least one transistor, wherein forming the transistor includes;
forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween;
wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer; and
forming storage and access circuitry coupled to the number of memory cells. - View Dependent Claims (21, 22)
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23. A method of forming an electronic system, comprising:
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forming a memory device coupled to a processor, wherein forming the memory device includes forming a number of memory cells, each cell including at least one transistor, wherein forming the transistor includes;
forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween;
wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer; and
forming storage and access circuitry coupled to the number of memory cells. - View Dependent Claims (24, 25, 26)
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Specification