Communication apparatus having a standard serial communication interface compatible with radio isolation

• US 20060141946A1
• Filed: 12/29/2004
• Published: 06/29/2006
• Est. Priority Date: 12/29/2004
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Inventors: Kulkarni, Satish S., Rush, Frederick A.
• Granted Patent: US 8,019,382 B2
• Time in Patent Office: Days
• US Class Current: 455/92
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 2215/066 by stopping a clock generator

Abstract

A communication apparatus including a digital processing circuit coupled to a radio frequency (RF) circuit and to a serial communications device. The serial communications device may be configured to buffer data communicated between the digital processing circuit and an external device. A portion of the serial communications device may be disabled during an active mode of operation of the RF circuit. The serial communications device may include a flow control logic circuit configured to control a data stream between the digital processing circuit and the external device while a portion of the serial communications device is disabled. In some embodiments, a portion of the digital processing circuit may be disabled during an active mode of operation of the RF circuit.

Claims

1. A communication apparatus comprising:

a radio frequency (RF) circuit configured to operate on a radio frequency signal;

a digital processing circuit coupled to the RF circuit; and

a serial communications device coupled to the digital processing circuit and configured to buffer data communicated between the digital processing circuit and an external device;

wherein at least a portion of the serial communications device is disabled during an active mode of operation of the RF circuit; and

wherein the serial communications device includes a flow control logic circuit configured to control a data stream between the communication apparatus and the external device while the at least a portion of the serial communications device is disabled.

2. The communication apparatus as recited in claim 1, wherein the serial communications device is a universal asynchronous receiver transmitter (UART).

3. The communication apparatus as recited in claim 1, wherein at least a portion of the digital processing circuit is disabled during an active mode of operation of the RF circuit.

4. The communication apparatus as recited in claim 3,

wherein the at least a portion of the digital processing circuit includes a processing unit configured to process data received from the external device;

and

wherein the at least a portion of the serial communications device includes an interface to the processing unit.

5. The communication apparatus as recited in claim 4, wherein the serial communications device includes a memory configured to buffer data received from the external device and transmit the data to the processing unit via the interface.

6. The communication apparatus as recited in claim 5, wherein the flow control logic circuit is configured to assert a flow control signal to the external device if a number of data characters buffered in the memory is greater than a threshold value.

7. The communication apparatus as recited in claim 5, wherein the flow control logic circuit is configured to de-assert a flow control signal to the external device if a number of data characters buffered in the memory is less than a threshold value.

8. The communication apparatus as recited in claim 5, wherein the flow control logic circuit is configured to detect a flow control character in a data stream from the external device at the same time as a previously received data character of the data stream is buffered in the memory.

9. The communication apparatus as recited in claim 8, wherein the flow control logic circuit is configured to convey the previously received data character to the processing unit for processing after detecting the flow control character.

10. The communication apparatus as recited in claim 8, wherein the flow control logic circuit is configured to detect the flow control character before a next data character of the data stream is buffered in the memory.

11. The communication apparatus as recited in claim 8, wherein the flow control logic circuit is configured to enable a transfer of data in the data stream to the external device in response to a detection of the flow control character.

12. The communication apparatus as recited in claim 4, wherein the serial communications device includes:

a first memory configured to temporarily buffer data received from the external device; and

a second memory configured to temporarily buffer data available for transmission to the external device.

13. The communication apparatus as recited in claim 12, wherein the flow control logic circuit is configured to transmit a flow control character to the external device if a number of data characters buffered in the first memory is greater than a threshold value.

14. The communication apparatus as recited in claim 13, wherein the flow control logic circuit is configured to transmit the flow control character before transmitting a next data character from the second memory to the external device.

15. The communication apparatus as recited in claim 12, wherein the flow control logic circuit is configured to transmit a flow control character to the external device if a number of data characters buffered in the first memory is less than a threshold value.

16. The communication apparatus as recited in claim 15, wherein the flow control logic circuit is configured to transmit the flow control character before transmitting a next data character from the second memory to the external device.

17. The communication apparatus as recited in claim 4, wherein the serial communications device includes a circuit configured to detect a baud rate of data received from the external device while the at least a portion of the serial communications device is disabled.

18. The communication apparatus as recited in claim 1, wherein the digital processing circuit includes a memory, and wherein the at least a portion of the serial communications device includes a direct memory access (DMA) interface coupled to the memory.

19. A method of operating a communication apparatus including a radio frequency (RF) circuit, a digital processing circuit, and a serial communications device configured to communicate data between the digital processing circuit and an external device, the method comprising:

buffering data communicated between the digital processing circuit and the external device within the serial communications device;

disabling at least a portion of the serial communications device during an active mode of operation of the RF circuit; and

controlling a data stream between the serial communications device and the external device while the at least a portion of the serial communications device is disabled.

20. The method as recited in claim 19, further comprising disabling at least a portion of the digital processing circuit during an active mode of operation of the RF circuit.

21. The method as recited in claim 19, further comprising:

receiving a data character in a first data stream from the external device;

buffering the data character;

detecting a presence of a flow control character in the first data stream;

enabling a second data stream to the external device if the flow control character is a start character; and

conveying the previously buffered data character to the digital processing circuit.

22. The method as recited in claim 19, further comprising:

receiving a data character in a first data stream from the external device;

buffering the data character;

detecting a presence of a flow control character in the first data stream;

disabling a second data stream to the external device if the flow control character is a stop character; and

conveying the previously buffered data character to the digital processing circuit.

23. The method as recited in claim 19, wherein the at least a portion of the serial communications device includes an interface to the digital processing circuit, further comprising:

enabling the at least a portion of the serial communications device;

transmitting data from the digital processing circuit to the serial communications device at a data rate that is greater than a data rate at which the data is transmitted from the serial communications device to the external device;

buffering the data within the serial communications device until a number of data characters buffered is greater than a threshold value;

disabling the at least a portion of the serial communications device; and

transmitting the data from the serial communications device to the external device while the at least a portion of the serial communications device is disabled.

24. The method as recited in claim 19, wherein the at least a portion of the serial communications device includes an interface to the digital processing circuit, further comprising:

enabling the at least a portion of the serial communications device;

receiving from the serial communications device to the digital processing circuit at a data rate that is greater than a data rate at which the data is received from the external device to the serial communications device, until a number of data characters buffered is less than a threshold value;

disabling the at least a portion of the serial communications device; and

buffering data received from the external device within the serial communications device while the at least a portion of the serial communications device is disabled.

25. A mobile phone comprising:

a radio frequency (RF) transceiver configured to operate on a radio frequency signal;

a digital processing circuit coupled to the RF transceiver; and

a serial communications device coupled to the digital processing circuit and configured to buffer data communicated between the digital processing circuit and an external device;

wherein the digital processing circuit includes a processing unit configured to process data received from the external device;

wherein the processing unit is disabled during an active mode of operation of the RF transceiver;

wherein at least a portion of the serial communications device is disabled during an active mode of operation of the RF transceiver;

wherein the serial communications device includes a flow control logic circuit configured to control a data stream between the mobile phone and the external device while the at least a portion of the serial communications device is disabled; and

wherein the RF transceiver, the digital processing circuit, and the serial communications device are fabricated on a single integrated circuit chip.