Autodetection of a PCI express device operating at a wireless RF mitigation frequency

• US 20060143338A1
• Filed: 12/29/2004
• Published: 06/29/2006
• Est. Priority Date: 12/29/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Martwick, Andrew W., Hunsaker, Mikal C., Vadivelu, Karthi
• Granted Patent: US 8,041,844 B2
• Time in Patent Office: Days
• US Class Current: 710/60
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

Claims

1. A computer system, comprising:

a processor; and

a chipset coupled to the processor, the chipset to support communication with a PCI Express compliant device at a first frequency, wherein the chipset is to communicate with a device at a second frequency, if the chipset fails to communicate with the device at the first frequency.

2. The computer system of claim 1, wherein the chipset comprises a switch to choose between transmitting data at the first frequency and transmitting data at the second frequency.

3. The computer system of claim 1, wherein the switch comprises a root port that implements an algorithm to auto-detect for a non-PCI Express compliant device to communicate with at the second frequency.

4. The computer system of claim 1, wherein the first frequency is 2.5 gigahertz.

5. The computer system of claim 1, wherein the second frequency is one-third the speed of the first frequency.

6. A computer system, comprising:

a microprocessor;

a controller hub coupled to the microprocessor; and

a device wirelessly coupled to the controller hub;

the controller hub having a root port with a transmitter and a receiver, wherein the root port attempts to identify bit transition edges and determine symbol boundaries at a first frequency of data communicated by the device, and wherein upon failing to identify bit transition edges and determine symbol boundaries at the first frequency, the root port steers the receiver to attempt to determine symbol boundaries at a second frequency.

7. The computer system of claim 6, wherein the controller hub further comprises:

a phased locked loop to generate a first clock signal at the first frequency;

a clock divider to divide the first clock signal by an integer to generate a second clock signal at the second frequency;

a wireless extension state machine to provide a first signal upon failing to identify bit transition edges and determine symbol boundaries at the first frequency; and

a multiplexer to select between the first and second clock frequency for at least the receiver, wherein the first clock signal is selected by default and the second clock signal is selected if the first signal is provide by the wireless extension state machine.

8. The computer system of claim 6, wherein the first frequency is a multiple of 2.5 GHz and the second frequency is ⅓

of the first frequency.

9. The computer system of claim 6, wherein if the receiver determines symbol boundaries at the second frequency, the transmitter is steered to the second frequency.

10. An apparatus, comprising:

a receive circuit interface to receive data;

a receive physical layer coupled to the receive circuit interface to look for bit patterns; and

a first state machine coupled to the receive physical layer to detect an endpoint device connected to the receive circuit interface.

11. The apparatus of claim 10, further comprising:

a second state machine coupled to the first state machine to select a first input clock for the receive physical layer.

12. The apparatus of claim 11, wherein the second state machine selects a first input clock for a transmit physical layer.

13. The apparatus of claim 12, wherein a transmit circuit interface is coupled to the transmit physical layer to transmit data to the endpoint device.

14. The apparatus of claim 10, wherein the first state machine determines whether the endpoint device is PCI Express compliant.

15. The apparatus of claim 14, wherein the second state machine selects a second input clock for the receive physical layer if the endpoint device is not PCI Express compliant.

16. The apparatus of claim 15, wherein the receive physical layer attempts to determine symbol boundaries with a data bit pattern at a frequency of the second input clock.

17. The apparatus of claim 16, wherein the second state machine selects a second input clock for the transmit physical layer if the receive physical layer determines symbol boundaries with the data bit pattern at the frequency of the second input clock.

18. The apparatus of claim 17, wherein the first state machine determines whether the endpoint device is operating at 833 megahertz frequency.

19. A method, comprising:

transmitting data from a transmitter in a PCI Express port at a first frequency;

clocking a receiver at the first frequency;

attempting to lock onto specific bits within a bit-stream and to identify symbol boundaries within a bit pattern received by the receiver at a first frequency; and

clocking the receiver at a second frequency, if the receiver does not lock onto specific bits within the bit-stream and the receiver does not identify symbol boundaries within the bit pattern after N attempts, wherein N is an integer greater than one.

20. The method of claim 19, further comprising completing link negotiation, if the receiver locks onto specific bits within a bit-stream and the receiver identifies symbol boundaries within a bit pattern received by the receive.

21. The method of claim 19, wherein symbol boundaries within a bit pattern are determined by identifying a unique symbol.

22. The method of claim 19, further comprising:

attempting to determine symbol boundaries within a bit pattern at the second frequency.

23. The method of claim 22, further comprising:

attempting to determine symbol boundaries within a bit pattern at the first frequency, if the attempts to determine symbol boundaries within a bit pattern at the second frequency were not successful within N attempts; and

transmitting data from the transmitter at the second frequency, if the attempts to determine symbol boundaries within a bit pattern at the second frequency were successful.

24. The method of claim 23, further comprising:

executing a training sequence at the second frequency.

25. The method of claim 24, further comprising:

executing a training sequence at the first frequency, if the PCI Express port fails to train at the second frequency.

26. The method of claim 24, further comprising:

completing link negotiation if the PCI Express port trains at the second frequency.

27. The method of claim 19, wherein the first frequency is 2.5 gigahertz.

28. The method of claim 19, wherein the second frequency is less than the first frequency.