System, method, and apparatus for extended serial peripheral interface

• US 20060143348A1
• Filed: 12/29/2004
• Published: 06/29/2006
• Est. Priority Date: 12/29/2004
• Status: Abandoned Application

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Wilson, Matthew T., Ross, Stephen R.
• Application Number:
  US11/025,713
• Publication Number:
  US 20060143348A1
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A system, method, and apparatus for interchip communication between an extended serial peripheral interface (EPSI) master (210) chip having clocking capability and an EPSI slave (310) chip is disclosed. The method comprises the master chip selecting a slave chip (402), the master clocking data into the slave chip from the master chip and at the same time clocking data from the slave chip into the master chip (404), and processing the clocked in data to negotiate further data transfer (406) between the master chip and the slave chip. Selection of a slave chip by the master chip may also take place in response to an interrupt received by the master chip from the slave chip (502), with the master then clocking data in both directions (504) to negotiate further data transfer (506) between the master chip and the slave chip.

Claims

1. A method for serial interchip communication between a master chip having clocking capability and a slave chip, the method comprising:

the master chip asserting a chip select, thereby selecting the slave chip;

the slave chip issuing an interrupt to the master chip;

clocking a slave message into the master chip from the slave chip;

clocking a master message into the slave chip from the master chip; and

processing the slave message and the master message to negotiate data flow between the master chip and the slave chip.

2. The method of claim 1 wherein the slave message comprises a byte specifying a message type.

3. The method of claim 1 wherein the master message comprises a byte specifying a message type.

4. The method of claim 1, further comprising:

clocking slave-to-master data into the master chip from the slave chip; and

clocking master-to-slave data into the slave chip from the master chip;

wherein the master chip controls flow of slave-to-master data from the slave chip by clocking, and flow of master-to-slave data from the master chip to the slave chip takes place according to the negotiated data flow.

5. The method of claim 4, wherein the slave message comprises at least one byte specifying a number of bytes in the slave-to-master data.

6. The method of claim 4, wherein the slave message comprises at least one byte specifying a first candidate size for the master-to-slave data.

7. The method of claim 6, wherein:

the master message comprises at least one byte specifying a second candidate size for the master-to-slave data; and

the master-to-slave data is of a size which is a minimum of the first candidate size and the second candidate size.

8. A system for serial interchip communication, comprising:

a master module;

a slave module;

a chip select line between the master module and the slave module for control of the slave module by the master module;

a clock line between the master module and the slave module for control of the slave module by the master module; and

an interrupt line between the master module and the slave module that provides capability for the slave module to interrupt the master module.

9. The system of claim 8 wherein master-to-slave data and slave-to-master data are processed, further comprising:

a Master-Out-Slave-In line between the master module and the slave module; and

a Master-In-Slave-Out line between the master module and the slave module;

wherein flow of the master-to-slave data across the Master-Out-Slave-In line and flow of the slave-to-master data across the Master-In-Slave-Out line are negotiated by a flow control protocol.

10. The system of claim 9, wherein the flow control protocol comprises a master message from the master module to the slave module and the master message comprises a byte specifying a message type.

11. The system of claim 10, wherein the flow control protocol further comprises a slave message from the slave module to the master module and the slave message comprises a byte specifying a message type.

12. The system of claim 11, wherein the master message further comprises at least one byte specifying a first candidate size for the master-to-slave data.

13. The system of claim 12, wherein:

the slave message further comprises at least one byte specifying a second candidate size for the master-to-slave data; and

the master-to-slave data is of a size which is a minimum of the first candidate size and the second candidate size.

14. The system of claim 11, wherein the slave message comprises at least one byte specifying a number of bytes in the slave-to-master data.

15. An apparatus, comprising:

a master device having connections for CS, CLK, MOSI, MISO, and IRQ signals;

a slave device having connections for CS, CLK, MOSI, MISO, and IRQ signals;

a control line connecting the master CS connection with the slave CS connection;

a control line connecting the master CLK connection with the slave CLK connection;

a control line connecting the master IRQ connection with the slave IRQ connection;

a data line connecting the master MOSI connection with the slave MOSI connection;

a data line connecting the master MISO connection with the slave MISO connection;

wherein;

the CS connection is utilized by the master device to enable the slave device;

the CLK connection is utilized by the master device to clock data flow between the master device and the slave device;

the IRQ connection is utilized by the slave device to alert the master device that the slave device has data to send to the master device;

the IRQ connection is further utilized by the slave device to alert the master device that the slave device is ready to accept data from the master device;

the MOSI connection is utilized to pass data from the master device to the slave device; and

the MISO connection is utilized to pass data from the slave device to the master device.

16. The apparatus of claim 15, wherein the CS, CLK, MOSI, MISO, and IRQ signals comprise a flow control protocol.

17. The apparatus of claim 16, wherein the flow control protocol comprises bytes specifying message type.

18. The apparatus of claim 16 wherein the flow control protocol comprises bytes specifying a number of bytes as a candidate size for the data across the MOSI connection.

19. The apparatus of claim 16 wherein the flow control protocol comprises bytes specifying a size for the data across the MISO connection.

20. An apparatus as recited in claim 15, wherein the apparatus is a cellular telephone.