System, method, and apparatus for extended serial peripheral interface
First Claim
1. A method for serial interchip communication between a master chip having clocking capability and a slave chip, the method comprising:
- the master chip asserting a chip select, thereby selecting the slave chip;
the slave chip issuing an interrupt to the master chip;
clocking a slave message into the master chip from the slave chip;
clocking a master message into the slave chip from the master chip; and
processing the slave message and the master message to negotiate data flow between the master chip and the slave chip.
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Abstract
A system, method, and apparatus for interchip communication between an extended serial peripheral interface (EPSI) master (210) chip having clocking capability and an EPSI slave (310) chip is disclosed. The method comprises the master chip selecting a slave chip (402), the master clocking data into the slave chip from the master chip and at the same time clocking data from the slave chip into the master chip (404), and processing the clocked in data to negotiate further data transfer (406) between the master chip and the slave chip. Selection of a slave chip by the master chip may also take place in response to an interrupt received by the master chip from the slave chip (502), with the master then clocking data in both directions (504) to negotiate further data transfer (506) between the master chip and the slave chip.
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Citations
20 Claims
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1. A method for serial interchip communication between a master chip having clocking capability and a slave chip, the method comprising:
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the master chip asserting a chip select, thereby selecting the slave chip;
the slave chip issuing an interrupt to the master chip;
clocking a slave message into the master chip from the slave chip;
clocking a master message into the slave chip from the master chip; and
processing the slave message and the master message to negotiate data flow between the master chip and the slave chip. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system for serial interchip communication, comprising:
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a master module;
a slave module;
a chip select line between the master module and the slave module for control of the slave module by the master module;
a clock line between the master module and the slave module for control of the slave module by the master module; and
an interrupt line between the master module and the slave module that provides capability for the slave module to interrupt the master module. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An apparatus, comprising:
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a master device having connections for CS, CLK, MOSI, MISO, and IRQ signals;
a slave device having connections for CS, CLK, MOSI, MISO, and IRQ signals;
a control line connecting the master CS connection with the slave CS connection;
a control line connecting the master CLK connection with the slave CLK connection;
a control line connecting the master IRQ connection with the slave IRQ connection;
a data line connecting the master MOSI connection with the slave MOSI connection;
a data line connecting the master MISO connection with the slave MISO connection;
wherein;
the CS connection is utilized by the master device to enable the slave device;
the CLK connection is utilized by the master device to clock data flow between the master device and the slave device;
the IRQ connection is utilized by the slave device to alert the master device that the slave device has data to send to the master device;
the IRQ connection is further utilized by the slave device to alert the master device that the slave device is ready to accept data from the master device;
the MOSI connection is utilized to pass data from the master device to the slave device; and
the MISO connection is utilized to pass data from the slave device to the master device. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification