Predictive early write-back of owned cache blocks in a shared memory computer system

• US 20060143406A1
• Filed: 12/27/2004
• Published: 06/29/2006
• Est. Priority Date: 12/27/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Mattina, Matthew, Chrysos, George Z.
• Granted Patent: US 7,624,236 B2
• Time in Patent Office: Days
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/084 with a shared cache

Abstract

A method for predicting early write back of owned cache blocks in a shared memory computer system. This invention enables the system to predict which written blocks may be more likely to be requested by another CPU and the owning CPU will write those blocks back to memory as soon as possible after updating the data in the block. If another processor is requesting the data, this can reduce the latency to get that data, reducing synchronization overhead, and increasing the throughput of parallel programs.

Claims

1. A method comprising:

requesting a block by a first processor;

determining if a second processor has the requested block;

transferring block to the first processor if the second processor does not have the requested block; and

immediately writing updated block to a memory by the first processor.

2. The method of claim 1 wherein the transferring block to the first processor further comprises sending an first signal to the first processor.

3. The method of claim 1 wherein the determining if the second processor has the requested block further comprises:

determining if the block is owned by the second processor; and

determining if the block is shared by the second processor, if the block is not owned by the second processor.

4. The method of claim 3, wherein the determining if the block is shared by the second processor further comprises sending an second signal to the first processor.

5. The method of claim 3 wherein the determining if the block is owned by the second processor further comprises sending an evict signal to the second processor.

6. The method of claim 5 further comprises updating block with recent stored data by the second processor.

7. The method of claim 6 further comprising:

setting a bit for an entry of the block in a buffer; and

extracting the updated block from the buffer.

8. The method of claim 7 further comprises writing the updated block to a memory by the second processor.

9. The method of claim 8 further comprising:

sending the updated block to the first processor by the memory; and

updating the updated block by the first processor.

10. The method of claim 9 further comprising:

requesting the updated block again by the first processor;

determining if the second processor has requested the updated block since the updated block was sent to the memory by the first processor; and

transferring updated block to the first processor.

11. The method of claim 10 further comprising sending the first signal to the first processor if the second processor has not requested the updated block since the updated block was sent to memory by the first processor.

12. The method of claim 11 further comprising:

updating the requested updated block by the first processor; and

holding the new updated block by the first processor.

13. The method of claim 10 further comprising sending a third signal to the first processor if the second processor had requested the updated block since the updated block was sent to the memory.

14. The method of claim 13 further comprising:

updating the requested updated block by the first processor; and

immediately writing the new updated block to the memory.

15. A first and second processors comprising:

a shared cache coupled to the first and second processors, wherein the shared cache determines ownership of a block of data;

a buffer located within each of the first and second processor, wherein the buffer stores most recent data for the block; and

wherein the first processor requests the block, if the block is shared by the second processor, the first processor obtains the block, updates the block and immediately writes the updated block to the shared cache.

16. The first and second processors of claim 15 wherein the buffer includes a bit for every block within the buffer.

17. The first and second processor of claim 16 wherein the block in the buffer is extracted when the bit is set.

18. The first and second processors of claim 15 wherein if the block requested by the first processor is shared by the second processor, the shared cache sends the second signal to the first processor.

19. The first and second processors of claim 15 wherein if the block requested by the first processor is not shared by the second processor, the shared cache sends the first signal to the first processor.

20. The first and second processors of claim 19 further comprising holding the updated block by the first processor.

21. A multiprocessor computer system comprising a plurality of nodes, each node from said plurality of nodes comprising:

a router to communicate with the plurality of nodes in the multiprocessor system;

at least first and second processors, wherein the first and second processor comprising;

a shared cache coupled to the first and second processors, wherein the shared cache determines ownership of a block of data,

a buffer located within each of the first and second processor, wherein the buffer stores most recent data for the block, and

wherein the first processor requests the block, if the block is shared by the second processor, the first processor obtains the block, updates the block and immediately writes the updated block to the shared cache,

a first interface to input/output devices; and

an audio input/output device coupled to the first interface.

22. The multiprocessor system of claim 21 wherein the buffer in the first and second processors includes a bit for every block within the buffer.

23. The multiprocessor system of claim 22 wherein the block in the buffer is extracted when the bit is set.

24. The multiprocessor system of claim 21 wherein if the block requested by the first processor is shared by the second processor, the shared cache sends the second signal to the first processor.

25. The multiprocessor system of claim 21 wherein if the block requested by the first processor is not shared by the second processor, the shared cache sends the first signal to the first processor.

26. The multiprocessor system of claim 25 further comprising holding the updated block by the first processor.

27. The multiprocessor system of claim 21 wherein the first interface is a point to point interface.