Aircraft in-flight entertainment system with a distributed memory and associated methods

• US 20060143662A1
• Filed: 12/28/2004
• Published: 06/29/2006
• Est. Priority Date: 12/28/2004
• Status: Active Grant

• Current Assignee: LiveTV LLC (Thales SA)
• Original Assignee: LiveTV LLC (Thales SA)
• Inventors: Frisco, Jeffrey A., Easterling, Scott D., Keen, Robert M.
• Granted Patent: US 9,509,937 B2
• Time in Patent Office: Days
• US Class Current: 725/76
• CPC Class Codes: H04N 21/41422 located in transportation means, e.g. personal vehicle arrangements specially adapted for transportation systems in broadcast systems H04H20/62
• CPC Class Codes: H04N 21/43615 Interfacing a Home Network, e.g. for connecting the client to a plurality of peripherals home Audio Video Interoperability [HAVI] data switching networks H04L12/2805
• CPC Class Codes: H04N 21/6143 involving transmission via a satellite
• CPC Class Codes: H04N 5/50 Tuning indicators; Automatic tuning control

Abstract

An aircraft in-flight entertainment (IFE) system includes a plurality of seat electronic boxes (SEBs) spaced throughout the aircraft. Each SEB comprises a memory including a shared memory portion for storing entertainment related data and an unshared memory portion. The SEBs cooperate with one another so that the entertainment related data in the shared memory portion of each SEB is available for at least one other SEB.

Claims

1. A method of calibrating a phase locked loop circuit, comprising

opening the loop of the phase locked loop circuit;

applying a known signal at at least one point of the phase locked loop circuit while the phase locked loop circuit is in an open loop condition;

measuring a frequency of at least one clock signal that results when the known signal is applied in the open loop condition; and

performing at least one calibration adjustment based upon a difference between the measured frequency and an expected frequency.

2. The method of claim 1 wherein the calibration adjustment provides corrective action for both a phase locked loop bandwidth and phase locked loop damping factor.

3. The method of claim 2 wherein the calibration adjustment corrects process and temperature variations.

4. The method of claim 1 wherein the known signal is applied as a charge pump output signal.

5. The method of claim 4 wherein the calibration adjustment comprises adjusting a closed loop charge pump output of the phase locked loop circuit.

6. The method of claim 1, wherein the known signal is a first known signal, the method further comprising:

applying a second known signal to the phase locked loop circuit while the phase locked loop circuit is in an open loop condition;

measuring a second frequency of at least one clock signal that results when the second known signal is applied in the open loop condition;

performing a second calibration adjustment based upon a difference between the second measured frequency and a second expected frequency.

7. The method of claim 6 wherein at least one of the first known signal and the second know signal is utilized to provide a loop bandwidth calibration.

8. The method of claim 6 wherein at least one of the first known signal and the second know signal is utilized to provide a damping factor calibration.

9. The method of claim 6 wherein the first known signal is utilized to provide a loop bandwidth calibration.

10. The method of claim 9 wherein the second known signal is utilized to provide a damping factor calibration.

11. The method of claim 6 wherein the first known signal is applied to an input of a phase detector and the calibration adjustment comprises adjusting the charge pump output during closed loop conditions of the phase locked loop circuit.

12. The method of claim 11 wherein the second known is signal is applied as an input to a charge pump and the second calibration adjustment comprises adjusting a closed loop condition of a loop filter.

13. The method of claim 1 wherein the known signal is applied to an input of a phase detector and the calibration adjustment comprises adjusting the charge pump output during closed loop conditions of the phase locked loop circuit.

14. The method of claim 11 wherein the known is signal is applied as an input to a charge pump and the calibration adjustment comprises adjusting a closed loop condition of a loop filter.

15. The method of claim 1 further comprising changing an oscillator gain proportionally to a feedback divider modulus.

16. A phase locked loop circuit, comprising:

a loop path within the phase locked loop circuit;

a switchable circuit element connected within the loop path to selectively open the loop path for performing a calibration of the phase locked loop circuit;

at least one known calibration signal coupled to the switchable circuit element, the known calibration signal selectively provided to the phase locked loop circuit for open loop measurements;

a frequency measurement circuit coupled to a clock signal generated by the phase locked loop circuit; and

calibration adjustment circuitry coupled to the frequency measurement circuit and at least one portion of the phase locked loop circuit, the calibration adjustment circuitry providing closed loop calibration of the phase locked loop circuit based upon open loop measurements.

17. The circuit of claim 16 wherein the known calibration signal is provided as a charge pump output.

18. The circuit of claim 16 wherein the known calibration signal is provided as at phase detector input.

19. The circuit of claim 16 wherein the known signal calibration signal is provided at a charge pump input.

20. The circuit of claim 16 wherein the calibration adjustment circuitry adjusts the charge pump output during closed loop conditions.

21. The circuit of claim 16 wherein the calibration adjustment circuitry adjusts an element of a loop filter.

22. The circuitry of claim 16 the known calibration signal is a first known calibration signal, further comprising a second known calibration signal, the second known calibration signal coupled to a second switchable circuit element, the second known calibration signal selectively provided to the phase locked loop circuit for open loop measurements.

23. The circuitry of claim 22 wherein the first known calibration signal is provided as at phase detector input and the second known signal calibration signal is provided at a charge pump input.

24. The circuitry of claim 22 wherein the wherein the calibration adjustment circuitry adjusts the charge pump output and an element of a loop filter during closed loop conditions.

25. The circuitry of claim 16, further comprising a controllable oscillator providing an output of the phase locked loop and feedback loop divider, the controllable oscillator having a gain that is adjustable in proportion to the feedback divider modulus.