Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation
First Claim
1. An integrated circuit comprising:
- a memory array having a first plurality of decoded lines traversing across the memory array in a first direction;
a pair of decoder circuits, one decoder circuit coupled to each of the plurality of decoded lines at one respective location along said decoded lines, and the other decoder circuit coupled to each of the plurality of decoded lines at another respective location along said decoded lines, both decoder circuits coupled to receive like address information.
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Accused Products
Abstract
In an embodiment of the invention an integrated circuit includes a memory array having a first plurality of decoded lines traversing across the memory array and a pair of dual-mode decoders, each decoder coupled to each of the plurality of decoded lines a respective location along said decoded lines, such as at opposite ends thereof. Both decoder circuits receive like address information. Normally both decoder circuits operate in a forward decode mode to decode the address information and drive a selected one of the decoded lines. During a test mode, one decoder is enabled in a reverse decode mode while the other decoder remains in a forward decode mode to verify proper decode operation and integrity of the decoded lines between the decoders.
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Citations
43 Claims
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1. An integrated circuit comprising:
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a memory array having a first plurality of decoded lines traversing across the memory array in a first direction;
a pair of decoder circuits, one decoder circuit coupled to each of the plurality of decoded lines at one respective location along said decoded lines, and the other decoder circuit coupled to each of the plurality of decoded lines at another respective location along said decoded lines, both decoder circuits coupled to receive like address information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An integrated circuit comprising:
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a memory array having a plurality of decoded lines traversing the memory array;
first and second dual-mode decoder circuits respectively coupled to each end of the decoded lines;
wherein, in a normal operating mode, both first and second decoders are configured to operate in a forward decode mode; and
wherein, in a first test mode, the first decoder is configured to operate in the forward decode mode, and the second decoder is configured to operate in a reverse decode mode. - View Dependent Claims (24, 25, 26, 27)
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28. A method for operating an integrated circuit including a memory array, said memory array including a plurality of decoded lines traversing across the memory array and further including a first and second decoder circuit respectively coupled to the plurality of decoded lines at respective different locations along said decoded lines, said method comprising the steps of:
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presenting address information to both the first and second decoder circuits;
in a normal operating mode, enabling both the first and second decoder circuits in a forward decode mode, thereby decoding the address information and driving a selected one of the plurality of decoded lines from said two different locations along said line. - View Dependent Claims (29, 30, 31, 32)
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33. A method for operating a memory array, said memory array including a plurality of decoded lines traversing across the memory array, said method comprising:
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providing a first decoder circuit coupled to each of the plurality of decoded lines at one respective location along said decoded lines, and a second decoder circuit coupled to each of the plurality of decoded lines at another respective location along said decoded lines, both first and second decoder circuits coupled to receive like address information. configuring the first decoder circuit in a forward decode mode to decode the address information presented thereto and drive a selected one of the plurality of decoded lines, and configuring the second decoder in a reverse decode mode to assert an output match signal if the selected one of decoded lines corresponds to the same address information. - View Dependent Claims (34, 35, 36)
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37. An integrated circuit comprising:
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a memory array including a plurality of decoded lines traversing across the memory array;
first means for decoding address information and driving a selected one of the plurality of decoded lines; and
second means distinct from said first means for comparing the address information and the selected one of the plurality of decoded lines, and driving an output match signal if the address information corresponds to the selected one of the plurality of decoded lines. - View Dependent Claims (38, 39, 40)
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- 41. A decoder circuit configured, in a first mode of operation, for decoding address information conveyed thereto and asserting a corresponding one of a plurality of decoded outputs, and further configured, in a second mode of operation, for asserting a match signal if the address information corresponds to an asserted one of the plurality of decoded outputs which is asserted external to the decoder circuit.
Specification