Field-effect transistor, its manufacturing method, and complementary field-effect transistor

• US 20060145245A1
• Filed: 02/09/2004
• Published: 07/06/2006
• Est. Priority Date: 02/07/2003
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Hara, Yoshihiro, Takagi, Takeshi
• Application Number:
  US10/544,486
• Publication Number:
  US 20060145245A1
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/783 comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET for thin film transistors H01L29/78612, H01L29/78696

Abstract

A field effect transistor comprises: a semiconductor substrate; a semiconductor layer provided on the semiconductor substrate, the semiconductor layer including a body region which contains an impurity of a first conductivity type; a gate dielectric film provided on the semiconductor layer; a gate electrode provided on the gate dielectric film; and a source region and a drain region provided in the semiconductor layer at positions below the sides of the gate electrode, the source region and the drain region containing an impurity of a second conductivity type. The gate electrode and the body region are electrically short-circuited. In the semiconductor layer except for the source region and the drain region, at least part of a junction portion bordering on the source region or the drain region contains the impurity of the first conductivity type with a higher concentration than in the body region except for junction portions bordering on the source region and the drain region.

Claims

1-14. -14. (canceled)

15. A field effect transistor, comprising:

a semiconductor substrate;

a semiconductor layer provided on the semiconductor substrate, the semiconductor layer including a body region which contains an impurity of a first conductivity type;

a gate dielectric film provided on the semiconductor layer;

a gate electrode provided on the gate dielectric film; and

a source region and a drain region provided in the semiconductor layer at positions below the sides of the gate electrode, the source region and the drain region containing an impurity of a second conductivity type,

wherein the gate electrode and the body region are electrically short-circuited, and

at least part of a junction portion between the source region and the body region contains the impurity of the first conductivity type with a higher concentration than in the junction portion between the drain region and the body region.

16. The field effect transistor of claim 15, wherein in the semiconductor layer except for the source region and the drain region, a junction portion bordering on a side surface of the source region contains the impurity of the first conductivity type with a higher concentration than in the body region except for the junction portion bordering on the source region.

17. The field effect transistor of claim 16, wherein:

the semiconductor layer includes a SiGe layer formed of Si_1-xGe_x (0<

x≦

1) on or above the body region; and

in the SiGe layer, a junction portion bordering on the source region contains the impurity of the first conductivity type with a higher concentration than in the body region except for the junction portion bordering on the source region.

18. The field effect transistor of claim 15, wherein the semiconductor substrate is a bulk substrate.

19. The field effect transistor of claim 15, wherein in the semiconductor layer except for the source region and the drain region, a junction portion bordering on a bottom of the source region contains the impurity of the first conductivity type with a higher concentration than in the body region except for the junction portion bordering on the source region.

20. The field effect transistor of claim 15, wherein the semiconductor layer includes a SiGe layer formed of Si_1-xGe_x (0<

x≦

1) on or above the body region.

21. The field effect transistor of claim 20, wherein the semiconductor layer includes:

a Si buffer layer provided on the body region;

the SiGe layer provided on the Si buffer layer; and

a Si cap layer provided on the SiGe layer and under the gate dielectric film.

22. The field effect transistor of claim 15, wherein the region at the junction portion bordering on the source region which contains the impurity of the first conductivity type with a higher concentration than in the body region except for the junction portion bordering on the source region has a thickness equal to or greater than 10 nm and equal to or smaller than 80 nm.

23. The field effect transistor of claim 15, wherein the semiconductor layer includes a silicon carbon layer formed of Si_1-xC_x (0<

x<

1) on or above the body region.

24. The field effect transistor of claim 15, wherein the semiconductor layer includes a silicon germanium carbon layer formed of Si_1-x-yGe_xC_y (0<

x<

1, 0<

y<

1, 0<

x+y<

1) on or above the body region.

28. The field effect transistor of claim 15, wherein the junction portion between the drain region and the body region further contains the impurity of the first conductivity type with a lower concentration than in at least part of the junction portion between the source region and the body region.

25. A complementary field effect transistor, comprising:

a first field effect transistor which includes a first semiconductor layer provided on a semiconductor substrate, the first semiconductor layer including a first body region that contains an impurity of a first conductivity type, a first gate dielectric film provided on the first semiconductor layer, a first gate electrode provided on the first gate dielectric film, the first gate electrode and the first body region being electrically short-circuited, and a first source region and a first drain region provided in the first semiconductor layer at positions below the sides of the first gate electrode, the first source region and the first drain region containing an impurity of a second conductivity type; and

a second field effect transistor which includes a second semiconductor layer provided on a semiconductor substrate, the second semiconductor layer including a second body region that contains an impurity of the second conductivity type, a second gate dielectric film provided on the second semiconductor layer, a second gate electrode provided on the second gate dielectric film, the second gate electrode and the second body region being electrically short-circuited, and a second source region and a second drain region provided in the second semiconductor layer at positions below the sides of the second gate electrode, the second source region and the second drain region containing an impurity of the first conductivity type,

wherein in the first semiconductor layer except for the first source region and the first drain region, at least part of a junction portion bordering on the first source region contains the impurity of the first conductivity type with a higher concentration than in the first body region except for a junction portion bordering on the first source region, and

in the second semiconductor layer except for the second source region, at least part of a junction portion bordering on the second source region contains the impurity of the second conductivity type with a higher concentration than in the second body region except for a junction portion bordering on the second source region.

26. A method for fabricating a field effect transistor which includes a semiconductor layer provided on a semiconductor substrate, the semiconductor layer including a first body region that contains an impurity of a first conductivity type, a gate dielectric film provided on the semiconductor layer, a gate electrode provided on the gate dielectric film, the gate electrode and the body region being electrically short-circuited, and a source region and a drain region provided in the semiconductor layer at positions below the sides of the gate electrode, the source region and the drain region containing an impurity of a second conductivity type, the method comprising the steps of:

(a) implanting an impurity of a first conductivity type in the semiconductor layer to form a first impurity region that contains the impurity of the first conductivity type with a higher concentration in a junction region of the semiconductor layer which borders on a bottom of the source region than in the body region except for a junction region which borders on the source region;

(b) implanting an impurity of a second conductivity type in the semiconductor layer to form the source region and the drain region; and

(c) implanting an impurity of a first conductivity type in the semiconductor layer to form a second impurity region that contains the impurity of the first conductivity type with a higher concentration in a junction region of the semiconductor layer which borders on a side surface of the source region than in the body region except for a junction region which borders on the source region.

27. The method of claim 26, further comprising, prior to steps (b) and (c), step (d) of forming the gate electrode above the semiconductor layer,

wherein at steps (b) and (c) a common resist mask is used, and ion implantation is performed using the gate electrode as a mask.