High aspect-ratio PN-junction and method for manufacturing the same

• US 20060145307A1
• Filed: 12/30/2004
• Published: 07/06/2006
• Est. Priority Date: 12/30/2004
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Wu, Chao-I, Lee, Ming Hsiu
• Granted Patent: US 8,378,382 B2
• Time in Patent Office: Days
• US Class Current: 257/653
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes
• CPC Class Codes: H10B 99/16 comprising memory cells having diodes

Abstract

A semiconductor device having high-aspect-ratio PN-junctions is provided. The semiconductor device includes a conducting layer. The semiconductor device further includes a plurality of first doped regions formed over the conducting layer. The sidewalls of the doped regions are doped to form PN-junctions. The semiconductor device also includes a plurality of second doped regions over the first doped regions.

Claims

1. A semiconductor device comprising:

a conducting layer;

a plurality of regions associated with a first dopant formed over the conducting layer;

each of the plurality of regions associated with the first dopant, having at least two sidewalls doped with a second dopant; and

a plurality of regions associated with the second dopant formed over the regions associated with the first dopant.

2. The semiconductor device of claim 1, wherein the plurality of regions associated with the first dopant are P-regions and the plurality of regions associated with the second dopant are N-regions.

3. The semiconductor device of claim 1, wherein the plurality of regions associated with the first dopant are N-regions and the plurality of regions associated with the second dopant are P-regions.

4. The semiconductor device of claim 1, further comprising:

a plurality of gaps defined between the plurality of regions associated with the first dopant, wherein the gaps are filled with isolation material.

5. The semiconductor device of claim 1, further comprising:

a plurality of regions disposed within the gaps defined between the plurality of regions associated with the second dopant are filled with isolation material.

6. The semiconductor device of claim 4, wherein the isolation material is composed of oxide.

7. The semiconductor device of claim 1, wherein the first dopant is of N+ type.

8. A semiconductor device comprising:

a conducting layer;

a plurality of regions associated with a first dopant formed over the conducting layer;

an isolation layer formed over the plurality of regions associated with the first dopant, the isolation-layer being formed over at least two sidewalls of the plurality of regions associated with the first dopant, is doped with a second dopant; and

a plurality of regions associated with the second dopant formed over the regions associated with the first dopant such that the isolation-layer separates the plurality of regions associated with the first dopant and corresponding regions associated with the second dopant.

9. The semiconductor device of claim 8, further comprising:

a plurality of isolation regions separating both the first doped regions, and the second doped regions.

10. The semiconductor device of claim 8, wherein the plurality of regions associated with the first dopant are P-regions and the plurality of regions associated with the second dopant are N-regions.

11. The semiconductor device of claim 8, wherein the plurality of regions associated with the first dopant are N-regions and the plurality of regions associated with the second dopant are P-regions.

12. The semiconductor device of claim 8, wherein the isolation regions are comprised of oxides.

13. The semiconductor device of claim 8, wherein the isolation layer is comprised of antifuse oxide.

14. A method for manufacturing a semiconductor device comprising:

providing a conducting layer;

forming a plurality of first doped regions over the conducting layer wherein each of the plurality of first doped regions are defined within four sidewalls;

doping at least two opposing sidewalls of the four sidewalls to generate PN-junctions; and

forming a plurality of second-doped regions over the first doped regions.

15. The method for manufacturing a semiconductor device of claim 14, further comprising:

forming oxide regions within gaps defined between the plurality of first doped regions.

16. The method for manufacturing a semiconductor device of claim 14, wherein the method of operation of doping at least two opposing sidewalls includes defining spacers at the at least two opposing sidewalls.

17. The method for manufacturing a semiconductor device of claim 14, wherein the first doped regions are P regions and the second doped regions are N regions.

18. The method for manufacturing a semiconductor device of claim 14, wherein the first doped regions are N regions and the second doped regions are P regions.

19. A method for manufacturing a semiconductor device comprising:

providing a conducting layer;

forming a plurality of first doped regions over the conducting layer, wherein each of the plurality of first doped regions are defined within four sidewalls;

forming an isolation-layer over the plurality of first doped regions and exposed surfaces of the conducting layer;

doping at least two sidewalls of the four sidewalls with a second dopant; and

forming a plurality of second doped regions over portions of the isolation layer defined above the plurality first doped regions.

20. The method of claim 19, further comprising:

forming the isolation layer of antifuse oxide.