Wafer level test head

• US 20060145715A1
• Filed: 01/06/2005
• Published: 07/06/2006
• Est. Priority Date: 01/06/2005
• Status: Abandoned Application

• Current Assignee: Peter C. Salmon
• Original Assignee: Peter C. Salmon
• Inventors: Salmon, Peter C.
• Application Number:
  US11/031,219
• Publication Number:
  US 20060145715A1
• Time in Patent Office: Days
• US Class Current: 324/750.60
• CPC Class Codes: G01R 1/07357 with flexible bodies, e.g. buckling beams
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A test head is described for simultaneous test and/or simultaneous burn-in of all of the chips on a semiconductor wafer, including high powered microprocessor chips. A test execution wafer is attached to a test pedestal with connections for power plus an interface to a test support computer. Mounted on the test execution wafer are all of the IC chips required to implement test circuits, power distribution, local memory, temperature sensing, and communication interfaces. Advanced flip chip connectors are preferably employed for assembling the test execution wafer; they enable rework of any chips that prove defective. Embedded in the test execution wafer are general purpose interconnection circuits plus through-wafer connectors. A test socket employing wells filled with liquid metal is provided on the back side of the test execution wafer. The wafer under test is bumped at the I/O pads, and the bumps are inserted into the wells filled with liquid metal. By circulating water or other cooling fluid against the back side of the wafer under test, a cooling rate of 20,000 watts or more can be applied.

Claims

1. A test head for test or burn-in of semiconductor wafers comprising:

a test pedestal having connections to a power source and a test support computer;

a test execution wafer mounted on said test pedestal and connected to said power source and to said test support computer;

said test execution wafer including both mounted integrated circuit chips and embedded circuits for executing test functions and/or burn-in;

said test execution wafer also including a socket for connecting to a wafer under test; and

,

said socket comprises an array of wells filled with a conductive fluid or paste.

2. The test head of claim 1 wherein said conductive fluid or paste is a liquid metal.

3. The test head of claim 1 and including a cooling chamber that attaches to said test pedestal.

4. The test head of claim 3 and including means for circulating a cooling fluid through said cooling chamber.

5. The test head of claim 1 wherein said circuits for executing said test or said burn-in include registers and comparators and digitally controlled power distribution devices.

6. The test head of claim 1 wherein said circuits for executing said test or said burn-in include test controllers, communication interfaces, local memory, and temperature sensors.

7. A method for simultaneously testing all of the die on a semiconductor wafer under test comprising the steps of;

a) providing a test execution wafer having attached integrated circuit chips containing test circuits;

b) providing a multi-pin connector between said test execution wafer and said wafer under test;

c) attaching said semiconductor wafer under test to said test execution wafer using said multi-pin connector;

d) simultaneously testing all of said integrated circuit chips on said semiconductor wafer using said test circuits, and recording the test results; and

,

e) communicating said test results to a test operator.

8. The method of claim 7 wherein said each of said pins of said connector comprises a conductive bump inserted into a well filled with a conductive fluid or paste.

9. The method of claim 7 wherein said test circuits include circuits for metering and distributing power.

10. The method of claim 7 and including the step of providing a circulating coolant fluid in contact with said semiconductor wafer under test.

11. The method of claim 7 and including the step of simultaneous burn-in of all of said die on said wafer under test, said burn-in step including the adjustment of operating temperature and voltage.

12. A test system for testing and/or burning-in semiconductor wafers comprising:

a test support computer including a test controller, said test support computer under control of a test operator;

a test head for accepting said semiconductor wafers, said test head in communication with said test controller; and

,

wherein said test head includes a test socket comprising wells filled with a conductive fluid or paste.

14. The test systems of claim 12 and 13 wherein said conductive fluid or paste is a liquid metal.

13. A test system for testing and/or burning-in semiconductor wafers comprising:

a test support computer including a test controller, said test support computer under control of a test operator;

a subsystem for cooling and circulating coolant, under control of said test controller;

a test head for accepting said semiconductor wafers, said test head in communication with said test controller; and

,

wherein said test head includes test execution circuits and test support circuits, a test socket comprising wells filled with a conductive fluid or paste, and a chamber for circulating said coolant fluid.

15. In a test head for testing and/or burning-in semiconductor wafers, a test execution wafer including both mounted integrated circuit chips and embedded circuits for executing test functions;

and,

a socket comprising an array of wells filled with conductive fluid or paste for detachably connecting to a wafer under test.

16. A test execution wafer as in claim 15 wherein said conductive fluid is a metal.