Liquid crystal panel and liquid crystal display device having the same

• US 20060145977A1
• Filed: 06/29/2005
• Published: 07/06/2006
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Choo, Kyo Seop, Lee, Hyun Joo
• Granted Patent: US 7,499,019 B2
• Time in Patent Office: Days
• US Class Current: 345/87
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

An LC panel and an LCD device having an LC panel are provided. The LC panel has a display part and a non-display part. Gate lines and data lines are arranged in a matrix on the display part. The gate lines include a first gate line group and a second gate line group. The first gate line group extends from one end of the display part and does not overlap the extending data lines; the second gate line group extends from an opposite end of the display part and overlaps the extending data lines. The disclosed devices and methods of using such allow one to control signal delay times to the first and second gate line groups so as to improve image quality or prevent imaging defects.

Claims

1. An LC panel comprising:

a display part and a non-display part;

the display part having gate lines and data lines arranged thereon, the gate lines having a first gate line group and a second gate line group;

the non-display part, having gate lines and data lines extending from the display part;

wherein the first gate line group extends from one end of the display part and does not overlap the extending data lines; and

wherein the second gate line group extends from an opposite end of the display part and overlaps the extending data lines.

2. The LC panel of claim 1, wherein capacitance is generated between the overlapping second gate line group and the extending data lines.

3. The LC panel of claim 1, wherein capacitance is not generated in the first gate line group.

4. The LC panel of claim 1, wherein the length of the first gate line group is longer than that of the second gate line group or the line resistance of the first gate line group is greater then that of the second gate line group.

5. The LC panel of claim 1, wherein a signal delay in the first gate line group is generated by line resistance in the first gate line group and wherein a signal delay in the second gate line group is generated by line resistance in the second gate line group and by capacitance generated between the second gate line group and the extended data lines.

6. The LC panel of claim 1, wherein the signal delay generated by the first gate line group is substantially the same as the signal delay generated by the second gate line group.

7. A liquid crystal display device comprising:

an LC panel, the LC panel comprising;

a display part and a non-display part;

the display part having gate lines and data lines arranged thereon, the gate lines having a first gate line group and a second gate line group;

the non-display part, having gate lines and data lines extending from the display part;

wherein the first gate line group extends from one end of the display part and does not overlap the extending data lines; and

wherein the second gate line group extends from an opposite end of the display part and overlaps the extending data lines; and

a data driver electrically connected to the extending data lines.

8. The liquid crystal display device of claim 7, wherein capacitance is generated between the overlapping second gate line group and the extending data lines.

9. The liquid crystal display device of claim 7, wherein capacitance is not generated in the first gate line group.

10. The liquid crystal display device of claim 7, wherein the length of the first gate line group is longer than the length of the second gate line group or the line resistance of the first gate line group is greater then that of the second gate line group.

11. The liquid crystal display device of claim 7, wherein the signal delay to the first gate line group is primarily influenced by line resistance.

12. The liquid crystal display device of claim 7, wherein the signal delay to the first gate line group is not influenced by capacitance between first gate line group and the extending data lines.

13. The liquid crystal display device of claim 7, wherein the signal delay to the second gate line group is influenced by line resistance and the capacitance between the second gate line group and the extending data lines.

14. The liquid crystal display device of claim 7, wherein signal delay to the first gate line group is substantially the same as the signal delay to the second gate line group.

15. The liquid crystal display device of claim 7, wherein the gate driver is disposed on the LC panel.

16. The liquid crystal display device of claim 7, wherein the data driver is disposed on the LC panel.

17. A method for improving image quality in a liquid crystal display device, comprising:

a) providing a liquid crystal display device having an LC panel, a gate driver and a data driver;

the LC panel having a display part and a non-display part;

wherein the display part has gate lines and data lines arranged thereon, and wherein the gate lines include a first gate line group and a second gate line group;

wherein the non-display part includes gate lines and data lines extending from the display part; and

wherein the first gate line group extends from one end of the display part and does not overlap the extending data lines; and

wherein the second gate line group extends from an opposite end of the display part and overlaps the extending data lines;

b) supplying scan signals from the gate driver to the first and second gate line groups to the gate lines in response to gate control signals from a controller; and

c) sufficiently controlling signal delay times to the first and second gate line groups to improve image quality or prevent at least one defect in image quality.

18. The method of claim 17, wherein the at least one defect includes a horizontal line appearing at the boundary between the first gate line group and the second gate line group.

19. The method of claim 17, wherein the delay times for generating scan signals to the first and second gate line groups do not substantially differ from one another.

20. The method of claim 17, wherein signal delay times to the first and second gate line groups are controlled by changing the line resistance in either the first gate line group, second gate line group, or both.

21. The method of claim 17, wherein the signal delay times to the first and second gate line groups are controlled by changing the length of the first gate line group, the second gate line group, or both.

22. The method of claim 17, wherein the signal delay times in the first gate line group and the second gate line group are controlled so that the influence of line resistance on signal delay time in the first gate line group is made substantially equivalent to the influence of line resistance and capacitance on signal delay in the second gate line group.