Shift register

• US 20060145999A1
• Filed: 12/06/2005
• Published: 07/06/2006
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Cho, Nam Wook, Yoon, Soo Young, Chun, Min Doo
• Granted Patent: US 7,595,783 B2
• Time in Patent Office: Days
• US Class Current: 345/100
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register for use with a liquid crystal display device includes a plurality of stages. A stage of the shift register includes a first controller, a second controller and an output buffer. The first controller charges and discharges a first node. The second controller charges and discharges a second node and a third node. The output buffer outputs a first output signal in response to the state of the first node and a second output signal in response to the state of the second and third nodes. The shift register may be adaptive to avoid a malfunction caused by a gate bias stress.

Claims

1. A shift register for use with a liquid crystal display device, a stage of the shift register comprising:

a first controller that charges and discharges a first node;

a second controller that charges and discharges a second node and a third node;

an output buffer that outputs a first output signal in response to the state of the first node and a second output signal in response to the state of the second and third nodes.

2. The shift register of claim 1, wherein the first controller comprises:

a first thin film transistor (“

TFT”

) activated in response to a start pulse;

a second TFT including a pair of TFTs that are alternately activated in response to the state of the second node and the third node; and

a third TFT activated in response to an output signal of a next stage of the shift register.

3. The shift register of claim 2, wherein the first TFT is coupled to the output buffer at the first node, and the pair of TFTs of the second TFT are coupled to the output buffer at the second and third nodes, respectively.

4. The shift register of claim 1, wherein the output buffer comprises:

a pull-up transistor that outputs the first output signal; and

a pair of pull-down transistors that output the second output signal alternately.

5. The shift register of claim 4, wherein one pull-down transistor is controlled to be activated in response to the state of the second node and the other pull-down transistor is controlled to be activated in response to the state of the third node.

6. The shift register of claim 5, wherein the pair of pull-down transistors are not activated simultaneously.

7. The shift register of claim 5, wherein the second node remains a low state during a frame that the other pull-down transistor is activated and the third node remains a low state during a frame that the one pull-down transistor is activated.

8. The shift register of claim 1, wherein the second controller comprises a first charger that charges the second node and a first discharger that discharges the second node.

9. The shift register of claim 8, wherein the second controller further comprises a second charger that charges the third node and a second discharger that discharges the third node.

10. The shift register of claim 8, wherein the second controller is coupled to the first controller and the output butter at the first, second and third nodes.

11. The shift register of claim 9, wherein the first charger comprises a first pair of TFTs that are connected in series and the first pair of TFTs are activated in response to a first clock signal and a first AC voltage.

12. The shift register of claim 11, wherein the first discharger comprises a second pair of TFTs that are connected in parallel and the second pair of TFTs are activated in response to the state of the first node and a strat pulse.

13. The shift register of claim 12, wherein the second charger comprises a third pair of TFTs that are connected in series and the third pair of TFTs are activated in response to the first clock signal and a second AC voltage.

14. The shift register of claim 13, wherein the second discharger comprises a fourth pair of TFTs that are connected in parallel and the fourth pair of TFTs are activated in response to the state of the first node and the strat pulse.

15. The shift register of claim 14, wherein the second controller further comprises a sixth TFT connected to the third node and activated in response to the first AC voltage and a seventh TFT connected to the second node and activated in response to the second AC voltage.

16. The shift register of claim 14, wherein the second controller further comprises a sixth TFT connected to the third node and activated by a state of the second node, and a seventh TFT connected to the second node and activated by a state of the third node.

17. The shift register of claim 1, wherein the first controller, the second controller and the output buffer comprise a plurality of TFTs of the same channel type.

18. The shift register of claim 17, wherein the plurality of TFTs comprise NMOS TFTs.

19. The shift register of claim 17, wherein the first controller, the second controller and the output buffer comprise a plurality of TFTs that are amorphous silicon TFTs.

20. A shift register having a plurality of stages that shifts a start pulse to supply the shifted start pulse as each output signal and a start pulse of a next stage, a stage of the shift register comprising:

first and second AC voltage supply lines for supplying first and second AC voltages having opposite polarities in first and second frames;

first and second DC voltage supply lines for supplying first and second DC voltages, respectively;

at least two clock signal supply lines for supplying at least two clock signals having different phases;

a pull-up thin film transistor controlled in response to the state of a first node to supply one of the clock signals to an output line;

first and second pull-down thin film transistors respectively controlled in response to the state of second and third nodes to alternately supply the second DC voltage to the output line in the first and second frames;

a first node controller for pre-charging and discharging the first node;

a second and third node charger for alternately charging the second and third nodes with the first DC voltage in the first and second frames under control of one of the clock signals and the first and second AC voltages; and

a second and third node discharger for alternately discharging the second and third nodes in the first and second frames.

21. The shift register of claim 20, wherein the second and third node charger comprises:

a first pair of TFTs connected in series between the first DC voltage supply line and the second node and controlled by the first AC voltage and the clock signal, respectively; and

,

a second pair of TFTs connected in series between the first DC voltage supply line and the third node and controlled by the second AC voltage and the clock signal, respectively.

22. The shift register of claim 21, wherein one of the first pair of TFTs is activated by the clock signal and the one TFT includes the same voltage at gate, source and drain electrodes thereof upon activation in a frame when the second node is charged.

23. The shift register of claim 22, wherein the one TFT includes a voltage at a gate electrode lower than a voltage at one of the source and drain electrodes upon deactivation, and the source and drain electrodes are connected to the first DC voltage supply line.

24. The shift register of claim 21, wherein one of the second pair of TFTs is activated by the clock signal and the one TFT includes the same voltage at gate, source and drain electrodes thereof upon activation in a frame when the third node is charged.

25. The shift register of claim 24, wherein the one TFT includes a voltage at a gate electrode lower than a voltage at one of the source and drain electrodes upon deactivation, and the source and drain electrodes are connected to the first DC voltage supply line.

26. The shift register of claim 20, wherein the at least two clock signal supply lines supply the phase inverted first and second clock signals to the pull-up TFT and the second and third node chargers, the first and second clock signals having an inverted phase.

27. A method for driving an output buffer of a shift register having a plurality of stages, comprising:

activating a first pull-down TFT in a first frame and deactivating a second pull-down TFT in the first frame;

activating a second pull-down TFT in a second frame and deactivating the first pull-down TFT in the second frame; and

deactivating a pull-up TFT when one of the first and second pull-down TFTs is activated.

28. The method of claim 27, further comprising activating the pull-up TFT in response to the state of a first node.

29. The method of claim 28, wherein activating the pull-up TFT comprises deactivating the first and second pull-down TFTs.

30. The method of claim 28, wherein activating the first pull-down TFT comprises activating the first pull-down TFT in response to the state of a second node.

31. The method of claim 30, wherein activating the second pull-down TFT comprises activating the second pull-down TFT in response to the state of a third node.

32. The method of claim 31, further comprising applying a high state to the second node and maintaining a low state at the third node.

33. The method of claim 31, further comprising applying a high state to the third node and maintaining a low state at the second node.

34. The method of claim 31, further comprising applying a high state to the first node and maintaining a low state at the second and third nodes.