Liquid crystal display device and fabricating method thereof

• US 20060146216A1
• Filed: 06/28/2005
• Published: 07/06/2006
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul, Lim, Byoung Ho, Ahn, Jae Jun
• Granted Patent: US 7,580,106 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A liquid crystal display device and a fabricating method thereof for simplifying a process are disclosed. A liquid crystal display device comprising first and second substrates; a gate line on the first substrate; a gate insulating film on the first substrate; a data line crossing the gate line to define a pixel area; a pixel hole in the pixel area; a pixel electrode formed of a transparent conductive layer on the gate insulating film in the pixel hole in the pixel area; and a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, wherein the semiconductor layer overlaps with a source/drain metal pattern including the data line, the source electrode, and the drain electrode; wherein the drain electrode protrudes from the semiconductor layer toward an upper portion of the pixel electrode, and the drain electrode connects to the pixel electrode; and wherein the semiconductor layer is removed from where it overlaps the transparent conductive layer.

Claims

1. A liquid crystal display device, comprising:

first and second substrates;

a gate line on the first substrate;

a gate insulating film on the first substrate;

a data line crossing the gate line to define a pixel area;

a pixel hole in the pixel area;

a pixel electrode formed of a transparent conductive layer on the gate insulating film in the pixel hole in the pixel area; and

a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer,

wherein the semiconductor layer overlaps with a source/drain metal pattern including the data line, the source electrode, and the drain electrode;

wherein the drain electrode protrudes from the semiconductor layer toward an upper portion of the pixel electrode, and the drain electrode connects to the pixel electrode; and

wherein the semiconductor layer is removed from where it overlaps the transparent conductive layer.

2. The liquid crystal display device as claimed in claim 1, further comprising a storage capacitor having a portion of the pixel electrode overlapping the gate line with the gate insulating film therebetween.

3. The liquid crystal display device as claimed in claim 1, further comprising:

a pad connected to at least one of the gate line and the data line,

wherein the pad includes;

a lower pad electrode on the substrate; and

an upper pad electrode in a contact hole that passes through the gate insulating film to expose the lower pad electrode and connected to the lower pad electrode.

4. The liquid crystal display device as claimed in claim 3, wherein the lower pad electrode is connected to the gate line.

5. The liquid crystal display device as claimed in claim 3, further comprising:

a data link extending from the lower pad electrode and overlapping with the data line; and

a contact electrode in a second contact hole that passes through the gate insulating film to expose the data link to connect the data link to the data line.

6. The liquid crystal display device as claimed in claim 5, wherein the contact hole of upper pad electrode extends along the data link to be integral to the second contact hole, and the upper pad electrode is integral to the contact electrode.

7. The liquid crystal display device as claimed in claim 5, wherein the upper pad electrode and the contact electrode borders with the gate insulating film enclosing the corresponding hole.

8. The liquid crystal display device as claimed in claim 5, wherein the pixel electrode, the upper pad electrode, and the contact electrode are formed of a transparent conductive layer.

9. The liquid crystal display device as claimed in claim 5, wherein a contact area between the data line and the contact electrode is within an area to be sealed by a sealant upon joining of the thin film transistor substrate with a second substrate.

10. The liquid crystal display device as claimed in claim 1, further comprising:

a data pad in contact holes that passes through the gate insulating film and connected to the data line.

11. The liquid crystal display device as claimed in claim 10, wherein the data pad is formed of a transparent conductive layer and borders with the gate insulating film enclosing the contact hole.

12. The liquid crystal display device as claimed in claim 1, further comprising a data pad formed of a transparent conductive layer on the gate insulating film and connected to the data line.

13. The liquid crystal display device as claimed in claim 10, wherein the data line protrudes from an area where it overlaps the semiconductor layer toward an upper portion of the data pad.

14. The liquid crystal display device as claimed in claim 12, wherein the data line protrudes from an area where it overlaps the semiconductor layer toward an upper portion of the data pad.

15. The liquid crystal display device as claimed in claim 13, wherein the data line is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

16. The liquid crystal display device as claimed in claim 14, wherein the data line is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

17. The liquid crystal display device as claimed in claim 1, wherein a channel of the thin film transistor further includes a surface layer oxidized by a plasma treatment.

18. The liquid crystal display device as claimed in claim 1, wherein the semiconductor layer and the source/drain metal pattern have a shape.

19. The liquid crystal display device as claimed in claim 3, further comprising a protective film on the substrate with an opening at a pad area provided with the pad.

20. The liquid crystal display device as claimed in claim 19, further comprising an alignment film on the protective film.

21. The liquid crystal display device as claimed in claim 20, wherein the protective film has the same pattern as the alignment film.

22. The liquid crystal display device as claimed in claim 19, wherein the protective film is formed in the same pattern as the second substrate.

23. The liquid crystal display device as claimed in claim 20, wherein the protective film is opened at the pad area.

24. The liquid crystal display device as claimed in claim 1, further comprising:

a color filter layer on the second substrate; and

a liquid crystal layer between the first and second substrates.

25. A method of fabricating a liquid crystal display device, comprising:

providing first and second substrates;

a first mask process of forming a gate line and a gate electrode connected to the gate line on the first substrate;

a second mask process forming a gate insulating film on the gate line and the gate electrode and a semiconductor layer, then defining a pixel hole that passes through the semiconductor layer in a pixel area, and forming a pixel electrode on the gate insulating film within the pixel hole; and

a third mask process including forming a source/drain metal pattern including a data line crossing the gate line to define the pixel area, a source electrode and a drain electrode on the first substrate, and exposing an active layer of the semiconductor layer to define a channel between the source electrode and the drain electrode.

26. The method as claimed in claim 25, wherein the third mask process further includes removing the semiconductor layer to except in the channel and where it overlaps the source/drain metal pattern and the gate insulating film.

27. The method as claimed in claim 25, wherein the third mask process includes:

forming a source/drain metal pattern including a data line and a drain electrode integral to the source electrode on the first substrate;

etching a semiconductor layer exposed through the source/drain metal pattern; and

exposing the active layer between the source electrode and the drain electrode to define the channel.

28. The method as claimed in claim 25, wherein the third mask process includes:

forming a source/drain metal layer on the first substrate;

forming photo-resist patterns having different thicknesses on the source/drain metal layer;

patterning the source/drain metal layer using the photo-resist patterns to form the source/drain metal pattern including the data line, the source electrode, and the drain electrode;

etching the semiconductor layer exposed through the photo-resist patterns; and

exposing the active layer between the source electrode and the drain electrode through the photo-resist patterns to form the channel.

29. The method as claimed in claim 25, wherein the second mask process further includes overlapping the pixel electrode with the gate line with the gate insulating film therebetween to form a storage capacitor.

30. The method as claimed in claim 25, wherein:

the first mask process further includes forming a lower pad electrode connected to the gate line; and

the second mask process further includes forming a contact hole to expose the lower pad electrode and forming an upper pad electrode connected to the lower pad electrode within the contact hole.

31. The method as claimed in claim 25, wherein:

the first mask process further includes forming a data link and a lower pad electrode to be connected to the data line on the first substrate; and

the second mask process further includes forming first and second contact holes to expose the lower pad electrode and the data link and forming an upper pad electrode connected to the lower pad electrode and a contact electrode connected to the data link and the data line within the corresponding contact hole.

32. The method as claimed in claim 31, wherein the first contact hole with the upper pad electrode extends along the data link to be integral to second contact hole, and the upper pad electrode is integral to the contact electrode.

33. The method as claimed in claim 30, wherein a transparent conductive pattern of at least one of the upper pad electrode and the contact electrode borders with the gate insulating film enclosing the corresponding hole.

34. The method as claimed in claim 31, wherein a transparent conductive pattern of at least one of the upper pad electrode and the contact electrode borders with the gate insulating film enclosing the corresponding hole.

35. The method as claimed in claim 31, wherein a contact area between the data line and the contact electrode is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

36. The method as claimed in claim 33, wherein a contact area between the data line and the contact electrode is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

37. The method as claimed in claim 25, wherein the second mask process further includes:

forming a contact hole that passes through the semiconductor layer and the gate insulating film and that overlaps with the data line; and

forming a pad connected to the data line within the contact hole.

38. The method as claimed in claim 37, wherein, when the contact hole passes through the gate insulating film, the pad borders with the gate insulating film enclosing the contact hole.

39. The method as claimed in claim 37, wherein the data line is within an area to be sealed by a sealant upon joining of the first substrates with the second substrate.

40. The method as claimed in claim 25, wherein the third mask process further includes surface treating the channel to oxidize the surface layer.

41. The method as claimed in claim 26, wherein the semiconductor layer and the source/drain metal pattern have a shape.

42. The method as claimed in claim 30, wherein the second mask process includes:

forming a photo-resist pattern having different thicknesses on the semiconductor layer using a partial transmitting mask;

forming the pixel hole and the contact hole using the photo-resist pattern as a mask;

forming a transparent conductive layer on the photo-resist pattern, and forming the corresponding transparent conductive pattern within the pixel hole and the contact hole; and

removing the photo-resist pattern formed with the transparent conductive film.

43. The method as claimed in claim 31, wherein the second mask process includes:

forming a photo-resist pattern having different thicknesses on the semiconductor layer using a partial transmitting mask;

forming the pixel hole and the contact hole using the photo-resist pattern as a mask;

forming a transparent conductive layer on the photo-resist pattern, and forming the corresponding transparent conductive pattern within the pixel hole and the contact hole; and

removing the photo-resist pattern formed with the transparent conductive film.

44. The method as claimed in claim 37, wherein the second mask process includes:

forming a photo-resist pattern having different thicknesses on the semiconductor layer using a partial transmitting mask;

forming the pixel hole and the contact hole using the photo-resist pattern as a mask;

forming a transparent conductive layer on the photo-resist pattern, and forming the corresponding transparent conductive pattern within the pixel hole and the contact hole; and

removing the photo-resist pattern formed with the transparent conductive film.

45. The method as claimed in claim 42, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned under the photo-resist pattern.

46. The method as claimed in claim 43, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned under the photo-resist pattern.

47. The method as claimed in claim 44, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned under the photo-resist pattern.

48. The method as claimed in claim 42, further comprising a fourth mask process of forming a protective film on the first substrate with the source/drain metal pattern and the removing the film at a pad area provided with the pad.

49. The method as claimed in claim 42, further comprising forming the protective film on the first substrate with the source/drain metal pattern except in a pad area provided with the pad.

50. The method as claimed in claim 42, further comprising:

forming the protective film on the first substrate with the source/drain metal pattern;

forming an alignment film on the protective film; and

removing the protective film at a pad area provided with the pad by an etching using the alignment film as a mask.

51. The method as claimed in claim 25, further comprising:

forming a protective film on the first substrate;

joining the second substrate to the first substrate by a sealant; and

removing the protective film at a pad area with the pad by an etching using the second substrate as a mask.

52. The method as claimed in claim 25, further comprising forming a liquid crystal layer between the first and second substrates.