Liquid crystal display device and fabricating method thereof

• US 20060146217A1
• Filed: 06/29/2005
• Published: 07/06/2006
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul, Lim, Byoung Ho, Ahn, Jae Jun
• Granted Patent: US 7,616,284 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

A liquid crystal display device, including: first and second substrates; a gate line on the first substrate; a data line crossing the gate line having a gate insulating film therebetween to define a pixel area; a pixel electrode formed of a transparent conductive film in a pixel hole passing through the gate insulating film in the pixel area; and a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer defining a channel between the source electrode and the drain electrode, wherein the semiconductor layer overlaps with a source and drain metal pattern including the data line, the source electrode and the drain electrode; and wherein the drain electrode protrudes from the semiconductor layer toward inside of the pixel electrode to be connected to the pixel electrode.

Claims

1. A liquid crystal display device, comprising:

first and second substrates;

a gate line on the first substrate;

a data line crossing the gate line having a gate insulating film therebetween to define a pixel area;

a pixel electrode formed of a transparent conductive film in a pixel hole passing through the gate insulating film in the pixel area; and

a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer defining a channel between the source electrode and the drain electrode,

wherein the semiconductor layer overlaps with a source and drain metal pattern including the data line, the source electrode and the drain electrode; and

wherein the drain electrode protrudes from the semiconductor layer toward inside of the pixel electrode to be connected to the pixel electrode.

2. The liquid crystal display device as claimed in claim 1, further comprising a storage electrode connected to the pixel electrode, wherein the storage electrode overlaps with the gate line having the gate insulating film to form a storage capacitor.

3. The liquid crystal display device as claimed in claim 2, wherein:

the semiconductor further overlaps the storage electrode and the gate insulating film; and

the storage electrode protrudes from where it overlaps the semiconductor layer toward the pixel hole to connect to the pixel electrode.

4. The liquid crystal display device as claimed in claim 3, wherein the drain electrode and the storage electrode are connected to each other above the pixel electrode.

5. The liquid crystal display device as claimed in claim 1, further comprising:

a pad connected to at least one of the gate line and the data line,

wherein the pad includes;

a lower pad electrode on the first substrate;

a contact hole passing through the gate insulating film to expose the lower pad electrode; and

an upper pad electrode in the contact hole connected to the lower pad electrode.

6. The liquid crystal display device as claimed in claim 5, wherein the lower pad electrode connects to the gate line.

7. The liquid crystal display device as claimed in claim 5, further comprising:

a data link extending from the lower pad electrode to overlap with the data line; and

a contact electrode in a second contact hole passing through the gate insulating film to expose the data link, thereby connecting the data link to the data line.

8. The liquid crystal display device as claimed in claim 7, wherein the contact hole with the upper pad electrode extends along the data link to be integral to the second contact hole, and the upper pad electrode is integral to the contact electrode.

9. The liquid crystal display device as claimed in claim 7, wherein the transparent conductive pattern including the pixel electrode, the upper pad electrode, and the contact electrode borders with the gate insulating film enclosing the corresponding hole.

10. The liquid crystal display device as claimed in claim 7, wherein an area where the data line contacts the contact electrode is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

11. The liquid crystal display device as claimed in claim 8, wherein an area where the data line contacts the contact electrode is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

12. The liquid crystal display device as claimed in claim 1, further comprising:

a data pad to be connected to the data line in a contact hole passing through the gate insulating film,

wherein the data pad borders with the gate insulating film enclosing the contact hole.

13. The liquid crystal display device as claimed in claim 12, wherein the data line is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

14. The liquid crystal display device as claimed in claim 1, wherein the channel of the thin film transistor includes a surface layer oxidized by a plasma surface treatment.

15. The liquid crystal display device as claimed in claim 1, wherein the semiconductor layer and the source and drain metal pattern have a shape.

16. The liquid crystal display device as claimed in claim 5, further comprising a protective film on the first substrate with an opening at a pad area.

17. The liquid crystal display device as claimed in claim 16, further comprising an alignment film on the protective film.

18. The liquid crystal display device as claimed in claim 17, wherein the protective film is formed with the same pattern as the alignment film.

19. The liquid crystal display device as claimed in claim 12, further comprising a protective film on the first substrate with an opening at a pad area.

20. The liquid crystal display device as claimed in claim 19, further comprising an alignment film on the protective film.

21. The liquid crystal display device as claimed in claim 20, wherein the protective film is formed with the same pattern as the alignment film.

22. The liquid crystal display device as claimed in claim 5, further comprising a protective film on the first substrate, the protective film having the same pattern as the second substrate and having an opening at a pad area.

23. The liquid crystal display device as claimed in claim 12, further comprising a protective film on the first substrate, the protective film having the same pattern as the second substrate and having an opening at a pad area.

24. The liquid crystal display device as claimed in claim 1, further comprising a liquid crystal layer between the first and second substrates.

25. A method of fabricating a liquid crystal display device, comprising:

providing first and second substrates;

a first mask process of forming a gate line and a gate electrode connected to the gate line on the first substrate;

a second mask process including forming a gate insulating film on the gate line and the gate electrode and forming a semiconductor layer, then defining a pixel hole that passes through the gate insulating film and the semiconductor layer in a pixel area, and forming a pixel electrode in the pixel hole; and

a third mask process including forming a source and drain metal pattern having a data line crossing the gate line to define the pixel area, a source electrode and a drain electrode on the first substrate, and exposing an active layer of the semiconductor pattern to define a channel between the source electrode and the drain electrode.

26. The method as claimed in claim 25, wherein the third mask process further includes removing the semiconductor layer except in the channel and where it overlaps the source and drain metal pattern and the gate insulating film.

27. The method as claimed in claim 26, wherein the third mask process includes:

forming a source and drain metal pattern including a data line and a drain electrode integral to the source electrode on the first substrate;

etching a semiconductor layer exposed through the source and drain metal pattern; and

exposing the active layer between the source and drain electrodes to define the channel.

28. The method as claimed in claim 26, wherein third mask process includes:

forming a source and drain metal layer on the first substrate;

forming photo-resist patterns having a different thicknesses on the source and drain metal layer;

patterning the source and drain metal layer using the photo-resist patterns to form the source and drain metal pattern including the data line and the drain electrode being integral to the source electrode;

etching a semiconductor layer exposed through the photo-resist patterns; and

exposing the active layer between the source and drain electrodes through the photo-resist patterns to form the channel.

29. The method as claimed in claim 25, wherein the third mask process further includes forming a storage electrode overlapping with the gate line to form a storage capacitor and connected to the pixel electrode.

30. The method as claimed in claim 25, wherein:

the semiconductor further overlaps the storage electrode and the gate insulating film; and

the drain electrode and the storage electrode protrude from where they overlap the semiconductor layer toward the pixel hole to connect to the pixel electrode.

31. The method as claimed in claim 25, wherein the drain electrode and the storage electrode are connected to each other above the pixel electrode.

32. The method as claimed in claim 25, wherein:

the first mask process further includes forming a lower pad electrode connected to the gate line; and

the second mask process further includes forming a contact hole to expose the lower pad electrode and forming an upper pad electrode connected to the lower pad electrode in the contact hole.

33. The method as claimed in claim 25, wherein:

the first mask process further includes forming a data link and a lower pad electrode to be connected to the data line on the first substrate; and

the second mask process further includes forming first and second contact holes to expose the lower pad electrode and the data link and forming an upper pad electrode connected to the lower pad electrode and a contact electrode connected to the data link and the data line in the corresponding contact hole.

34. The method as claimed in claim 33, wherein the first contact hole with the upper pad electrode extends along the data link to be integral to second contact hole, and the upper pad electrode is integral to the contact electrode.

35. The method as claimed in claim 33, wherein at least one of the pixel electrode, the upper pad electrode, and the contact electrode borders with the gate insulating film enclosing the corresponding hole.

36. The method as claimed in claim 33, wherein a contact area between the data line and the contact electrode is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

37. The method as claimed in claim 32, wherein at least one of the pixel electrode, the upper pad electrode, and the contact electrode borders with the gate insulating film enclosing the corresponding hole.

38. The method as claimed in claim 32, wherein a contact area between the data line and the contact electrode is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

39. The method as claimed in claim 25, wherein the second mask process further includes:

forming a contact hole passes through the semiconductor layer and the gate insulating film and overlaps with the data line; and

forming a pad connected to the data line in the contact hole.

40. The method as claimed in claim 39, wherein the pad borders with the gate insulating film enclosing the contact hole.

41. The method as claimed in claim 39, wherein the data line is within an area to be sealed by a sealant upon joining of the first substrate with the second substrate.

42. The method as claimed in claim 25, wherein the third mask process further includes surface treating of the channel of the thin film transistor to oxidize the surface layer.

43. The method as claimed in claim 26, wherein the semiconductor layer and the source/drain metal pattern have a shape.

44. The method as claimed in claim 32, wherein the second mask process includes:

forming a photo-resist pattern on the semiconductor layer;

forming the pixel hole and the contact hole using the photo-resist pattern as a mask;

forming a transparent conductive film on the photo-resist pattern, and forming the corresponding transparent conductive pattern in the pixel hole and the contact hole; and

removing the photo-resist pattern formed with the transparent conductive film.

45. The method as claimed in claim 44, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned under the photo-resist pattern.

46. The method as claimed in claim 33, wherein the second mask process includes:

forming a photo-resist pattern on the semiconductor layer;

forming the pixel hole and the contact hole using the photo-resist pattern as a mask;

forming a transparent conductive film on the photo-resist pattern, and forming the corresponding transparent conductive pattern in the pixel hole and the contact hole; and

removing the photo-resist pattern formed with the transparent conductive film.

47. The method as claimed in claim 46, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned under the photo-resist pattern.

48. The method as claimed in claim 39, wherein the second mask process includes:

forming a photo-resist pattern on the semiconductor layer;

forming the pixel hole and the contact hole using the photo-resist pattern as a mask;

forming a transparent conductive film on the photo-resist pattern, and forming the corresponding transparent conductive pattern in the pixel hole and the contact hole; and

removing the photo-resist pattern formed with the transparent conductive film.

49. The method as claimed in claim 48, wherein the semiconductor layer and the gate insulating film are over-etched such that the edges of the pixel hole and the contact hole are positioned under the photo-resist pattern.

50. The method as claimed in claim 32, further comprising a fourth mask process of forming a protective film on the first substrate and having an opening at a pad area.

51. The method as claimed in claim 33, further comprising a fourth mask process of forming a protective film on the first substrate and having an opening at a pad area.

52. The method as claimed in claim 39, further comprising a fourth mask process of forming a protective film on the first substrate and having an opening at a pad area.

53. The method as claimed claim 32, further comprising printing the protective film on the first substrate so as to have an opening at a pad area.

54. The method as claimed claim 33, further comprising printing the protective film on the first substrate so as to have an opening at a pad area.

55. The method as claimed claim 39, further comprising printing the protective film on the first substrate so as to have an opening at a pad area.

56. The method as claimed in claim 32, further comprising:

forming the protective film on the first substrate with the source and drain metal pattern;

forming an alignment film on the protective film; and

removing the protective film at a pad area with the pad by an etching process using the alignment film as a mask.

57. The method as claimed in claim 33, further comprising:

forming the protective film on the first substrate with the source and drain metal pattern;

forming an alignment film on the protective film; and

removing the protective film at a pad area with the pad by an etching process using the alignment film as a mask.

58. The method as claimed in claim 39, further comprising:

forming the protective film on the first substrate with the source and drain metal pattern;

forming an alignment film on the protective film; and

removing the protective film at a pad area with the pad by an etching process using the alignment film as a mask.

59. The method as claimed in claim 32, further comprising:

forming the protective film on the first substrate;

attaching the first and second substrates using a sealant; and

removing the protective film at a pad area with the pad by an etching process using the second substrate as a mask.

60. The method as claimed in claim 33, further comprising:

forming the protective film on the first substrate;

attaching the first and second substrates using a sealant; and

removing the protective film at a pad area with the pad by an etching process using the second substrate as a mask.

61. The method as claimed in claim 39, further comprising:

forming the protective film on the first substrate;

attaching the first and second substrates using a sealant; and

removing the protective film at a pad area with the pad by an etching process using the second substrate as a mask.

62. The method as claimed in claim 25, further comprising forming a liquid crystal layer between the first and second substrates.