Liquid crystal display device and fabricating method thereof

• US 20060146245A1
• Filed: 06/30/2005
• Published: 07/06/2006
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul, Lim, Byoung Ho, Ahn, Jae Jun
• Granted Patent: US 7,760,276 B2
• Time in Patent Office: Days
• US Class Current: 349/139
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

Disclosed is a thin film transistor substrate for a fringe filed switching type liquid crystal display device, and a fabrication method thereof, that reduces the number of required mask processes, and thus improves fabrication efficiency. The fabrication method involves three mask processes, wherein the masks are partial transmitting masks, and the resulting photo-resist patterns have varying thicknesses. By having photo-resist layers of varying thicknesses, structures can be formed in multiple etching steps using the same photo-resist pattern by incrementally removing the photo-resist according to its thickness. The thin film transistor substrate has a common line, a common electrode, a gate line and a gate electrode formed directly on the substrate. The common electrode overlaps the pixel electrode in the pixel area.

Claims

1. A liquid crystal display device, comprising:

first and second substrates;

a gate line on the first substrate;

a common line on the first substrate;

a common electrode on the fist substrate, wherein the common electrode is connected to the common line;

a gate insulating film on the gate line, the common line, and the common electrode;

a data line on the gate insulating film, wherein the data line crosses the gate line;

a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode, and a semiconductor layer having a channel between the source electrode and the drain electrode; and

a pixel electrode connected to the drain electrode, wherein the drain electrode overlaps a portion of the pixel electrode.

2. The device of claim 1, wherein the common line includes:

a first layer having a transparent conductive material; and

a second layer having a metal.

3. The device of claim 2, wherein the first layer includes ITO.

4. The device of claim 2, wherein the second layer includes Mo.

5. The device of claim 2, wherein the common electrode is formed by an extension of the transparent conductive material of the common line.

6. The device of claim 1, wherein the pixel electrode overlaps the common electrode.

7. The device of claim 1, further comprising a gate pad connected to the gate line, wherein the gate pad includes:

a lower pad electrode on the first substrate; and

an upper pad electrode in a contact hole passing through the gate insulating film to expose the lower pad electrode,

wherein the upper pad electrode is connected to the lower pad electrode.

8. The device of claim 1, further comprising a data pad connected to the data line, wherein the data pad includes:

a lower pad electrode provided on the first substrate; and

an upper pad electrode in a contact hole passing through the gate insulating film to expose the lower pad electrode,

wherein the upper pad electrode is connected to the lower pad electrode.

9. The device of claim 8, further comprising:

a data link extended from the lower pad electrode, wherein the data link overlaps the data line; and

a contact electrode in a second contact hole passing through the gate insulating film to expose the data link, wherein the contact electrode connects the data link to the data line.

10. The device of claim 1, further comprising a data pad formed of a transparent conductive layer in a contact hole passing through the gate insulating film, wherein the data pad is connected to the data line, wherein the data pad forms an interface with the gate insulating film enclosing the contact hole.

11. The device of claim 1, wherein the channel between the source electrode and the drain electrode includes an oxidized surface.

12. The thin film transistor substrate of claim 1, further comprising a protective film on the first substrate.

13. The thin film transistor substrate of claim 12, further comprising an alignment film on the protective film.

14. A method of fabricating a liquid crystal display device, comprising:

providing first and second substrates;

forming a gate line, a gate electrode connected to the gate line, a common line parallel to the gate line and a common electrode connected to the common line on the first substrate, using a first mask;

forming a gate insulating film and a semiconductor layer having a pixel hole through the semiconductor layer, and forming a pixel electrode overlapping the common electrode in the pixel hole, using a second mask; and

forming a source and drain metal pattern including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode connected to the pixel electrode, and a channel between the source electrode and the drain electrode, using a third mask.

15. The method of claim 14, wherein forming the gate line includes:

forming a first layer having a transparent conductor; and

forming a second layer having a metal.

16. The method of claim 14, wherein forming the common line and the common electrode includes:

forming a first layer having a transparent conductor to define the common line and the common electrode; and

forming a second layer having a metal on the first layer defining the common line.

17. The method of claim 14, wherein using the first mask includes:

forming a first conductive layer and a second conductive layer on the first substrate;

forming a photo-resist pattern having a first portion with a first thickness and a second portion having a second thickness;

performing a first etching to remove a portion of the first conductive layer and the second conductive layer corresponding to the photo-resist pattern;

removing the first portion of the photo-resist pattern; and

performing a second etching to remove a second portion of the second conductive layer corresponding to the second portion of the photo-resist pattern.

18. The method of claim 17, wherein removing a portion of the photo-resist pattern includes an ashing process using an oxygen (O₂) plasma.

19. The method of claim 17, wherein forming the first conductive layer and the second conductive layer includes:

forming a first conductive layer having ITO; and

forming a second conductive layer having Mo.

20. The method of claim 14, wherein using a third mask includes:

forming a source and drain metal layer;

forming a photo-resist pattern on the source/drain metal layer, the photo-resist pattern having a first portion with a first thickness and a second portion having a second thickness;

forming a source and drain metal pattern corresponding to the photo-resist pattern;

performing a first etching to remove the semiconductor layer exposed by the source and drain metal pattern;

removing the first portion of the photo-resist pattern; and

performing a second etching using the second portion of the photo-resist as a mask.

21. The method of claim 14, further comprising:

forming a lower pad electrode connected to at least one of the gate line and the common line, using the first mask;

forming a contact hole for exposing the lower pad electrode, using the second mask; and

forming an upper pad electrode connected to the lower pad electrode in the contact hole, using the second mask.

22. The method of claim 14, further comprising:

forming a protective film on the first substrate; and

forming an alignment film on the protective film.

23. The method of claim 22, wherein the protective film has an opening at a pad area by an etching using the alignment film as a mask.

24. The method of claim 22, wherein the protective film has a same pattern as the alignment film.

25. The method of claim 22, wherein the protective film has an opening at a pad area by an etching using the second substrate as a mask.

26. The method of claim 22, wherein the protective film has a same pattern as the second substrate.

27. The method of claim 14, further comprising forming a liquid crystal layer between the first and second substrates.