Integrated DRAM-NVRAM multi-level memory

• US 20060146594A1
• Filed: 03/03/2006
• Published: 07/06/2006
• Est. Priority Date: 08/27/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup, Forbes, Leonard
• Granted Patent: US 7,379,336 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Abstract

An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.

Claims

1. A method for operation of an integrated DRAM-NVRAM cell having a DRAM function and a NVRAM function, the cell comprising a DRAM gate, a NVRAM control gate, a DRAM source region, a NVRAM source region, a shared drain region, and a bitline coupled to the shared drain region, the method comprising:

applying a ground potential to the NVRAM source region;

applying a first voltage to the NVRAM control gate; and

applying a second voltage to the DRAM gate in order to read one of a plurality of data bits from the NVRAM function in response to the first voltage and the second voltage.

2. The method of claim 1 wherein the bitline is floating.

3. The method of claim 1 wherein when the first voltage is 0V and the second voltage is 0.8V, a first bit of the plurality of bits is read.

4. The method of claim 1 wherein when the first voltage is 1.2V and the second voltage is 0V, a second bit of the plurality of bits is read.

5. The method of claim 1 wherein the DRAM function operates as an access device for the NVRAM function.

6. The method of claim 1 wherein the bitline is coupled to adjacent drain regions of adjacent memory cells.

7. The method of claim 1 wherein the bitline couples a column of memory cells of a memory array.

8. A method for operation of an integrated DRAM-NVRAM cell having a DRAM function and a NVRAM function, the cell formed in a pillar and comprising a DRAM gate, a NVRAM control gate, a DRAM source region, a NVRAM source region, a shared drain region, and a bitline coupled to the shared drain region, the method comprising:

biasing the NVRAM source region with a voltage substantially equal to 0V;

biasing the NVRAM control gate with a first voltage; and

biasing the DRAM gate with a second voltage such that one of a plurality of data bits is read from the NVRAM function in response to the first and second voltages.

9. The method of claim 8 wherein during operation a floating body forms in the pillar.

10. The method of claim 8 wherein the NVRAM function is a substantially non-volatile memory function.

11. The method of claim 8 wherein the DRAM function is an access device for the NVRAM function.

12. The method of claim 8 wherein the NVRAM is adapted to store multiple data bits.

13. The method of claim 8 wherein biasing causes a depletion region to form around each source region.

14. The method of claim 13 wherein the depletion regions are substantially in contact such that a floating body is formed in the pillar.

15. The method of claim 8 wherein the pillar and trenches are formed on an SOI structure.

16. A method for operation of an integrated DRAM-NVRAM cell having a DRAM function and a NVRAM function, the cell formed in a pillar between two trenches and comprising a vertical DRAM gate, a vertical NVRAM control gate, a DRAM source region, a NVRAM source region, a shared drain region formed in the top of the pillar, and a bitline coupled to the shared drain region, the method comprising:

biasing the vertical NVRAM source region with a voltage substantially equal to 0V;

biasing the vertical NVRAM control gate with a first voltage; and

biasing the vertical DRAM gate with a second voltage such that one of a plurality of data bits is read from the NVRAM function in response to the first and second voltages.

17. The method of claim 16 wherein the DRAM function is an access device for the NVRAM function adapted to store the plurality of bits.

18. The method of claim 16 wherein the DRAM function is a volatile memory function.