Semiconductor device

• US 20060146623A1
• Filed: 02/28/2006
• Published: 07/06/2006
• Est. Priority Date: 02/04/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Sakata, Takeshi, Kanno, Yusuke, Mizuno, Hiroyuki, Oodaira, Nobuhiro, Watanabe, Takao
• Granted Patent: US 7,242,627 B2
• Time in Patent Office: Days
• US Class Current: 365/203
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

Claims

1. A semiconductor device, comprising a word line, a first bit line pair, a memory cell provided at an intersection of said word line and said first bit line pair, a second bit line pair, a switch circuit for coupling said first bit line pair and said second bit line pair, a sense amplifier including a first circuit connected to said first bit line pair and a second circuit connected to said second bit line pair, a first precharge circuit for precharging said first bit line pair to a first precharge potential and a second precharge circuit for precharging said second bit line pair to a second precharge potential, wherein

said second circuit amplifies one of said first bit line pair and one of said second bit line pair to a first potential and the other of said first bit line pair and the other of said second bit line pair to a second potential from a storage signal of said memory cell,

said first precharge potential is ranged between said first and second potentials, and

said second precharge potential is said second potential.

2-22. -22. (canceled)