Semiconductor device

• US 20060146634A1
• Filed: 01/04/2006
• Published: 07/06/2006
• Est. Priority Date: 01/05/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Osada, Kenichi, Kawahara, Takayuki
• Granted Patent: US 7,336,526 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.

Claims

1. A semiconductor device comprising:

a power supply terminal;

a plurality of word lines extending in a first direction;

a plurality of bit lines extending in a second direction and intersecting with said plurality of word lines;

a memory array including a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of bit lines;

a plurality of word drivers connected to each of said plurality of word lines;

a plurality of read circuits and write circuits connected to said plurality of bit lines; and

a power supply circuit that converts a power fed to said power supply terminal and supplies said power to internal circuits; and

a detect circuit detecting the variations in power supply potential,

wherein each of said plurality of memory cells has a selection element and a storage element alternately connected in series to corresponding one line of said plurality of bit lines,

wherein the control electrode of said selection element is connected to corresponding one line of said plurality of word lines,

wherein said storage element stores data according to the changes in resistance and allows rewriting the information by flowing electric current, and

wherein said selection element is unselected by said word lines, when said circuit for detecting the variations in power supply potential detects variations in power supply potential.

2. A semiconductor device according to claim 1,

wherein said detect circuit detects a voltage supplied to said power supply terminal as a variation in the power supply potential, and unselects said selection element by means of said word line in order to block the current path to said storage element.

3. A semiconductor device according to claim 1,

wherein said detect circuit detects that the potential of said power supply terminal dropped below a predetermined potential, and unselects said selection element by means of said word line in order to block the current path to said storage element.

4. A semiconductor device according to claim 1,

wherein said plurality of power supply circuits includes a voltage generator circuit to write data to said memory cells.

5. A semiconductor device according to claim 1,

wherein said plurality of power supply circuits comprises a first power supply circuit generating a first voltage to write first level data to said storage element, a second power supply circuit generating a second voltage to write second level data to said storage element, and a third power supply circuit generating a third voltage to read the data stored in said storage cell, and

wherein said second voltage is smaller than said first voltage and larger than said third voltage.

6. A semiconductor device according to claim 1,

wherein said power supply voltage to be applied to said power supply terminal is used to write the first level data to said storage element,

wherein said plurality of power supply circuits comprise a second power supply circuit generating a second voltage to write second level data to said storage element, and a third power supply circuit generating a third voltage to read the data stored in said storage element, and

wherein said second voltage is smaller than said first power supply voltage and larger than said third voltage.

7. A semiconductor device according to claim 1,

wherein said selection element is an N-channel MOS transistor.

8. A semiconductor device according to claim 1,

wherein said storage element is a phase change element.

9. A semiconductor device comprising

a power supply terminal;

a plurality of word lines extending in a first direction;

a plurality of bit lines extending in a second direction and intersecting with said plurality of word lines;

a memory array containing a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of bit lines;

a plurality of word drivers connected to each of said plurality of word lines;

a plurality of read circuits and write circuits connected to said plurality of bit lines;

a power supply circuit converting a power fed to said power supply terminal, and supplying said power to internal circuits; and

a detect circuit detecting the variations in power supply potential,

wherein each of said plurality of memory cells has a selection element and a storage element alternately connected in series to corresponding one line of said plurality of bit lines,

wherein the control electrode of said selection element is connected to corresponding one line of said plurality of word line,

wherein said storage element stores data according to the changes in resistance and allows rewriting the information by flowing electric current, and

wherein said bit line and said source line are interconnected to bypass the current to said storage element, when said detect circuit detects a variation in power supply potential.

10. A semiconductor device according to claim 9,

wherein said detect circuit detects a power supplied to said power supply terminal as a variation in the power supply potential, and connects said bit line and said source line to bypass the current to said storage element.

11. A semiconductor device according to claim 9,

wherein said detect circuit detects that the potential at said power supply terminal is below a predetermined potential, and interconnects said bit line and said source line to bypass the current to said storage element.

12. A semiconductor device according to claim 9,

wherein said plurality of power supply circuits include a voltage generator circuit to write data to said memory cell.

13. A semiconductor device according to claim 9, further comprising:

a first power supply circuit generating a first voltage to write first level data to said storage element;

a second power supply circuit generating a second voltage to write second level data to said storage element; and

a third power supply circuit generating a third voltage to read the data stored in said storage element,

wherein said second voltage is smaller than said first voltage and larger than said third voltage.

14. A semiconductor device according to claim 9,

wherein a first power supply voltage to be applied to said power supply terminal is used to write first level data;

wherein said plurality of power supply circuits include a second power supply circuit generating a second voltage to write second level data to said storage element, and a third power supply circuit generating a third power supply voltage to read the data stored in said storage element; and

wherein said second voltage is smaller than said first power supply voltage and larger than said third voltage.

15. A semiconductor device according to claim 9,

wherein said selection element is an N-channel MOS transistor.

16. A semiconductor device according to claim 9,

wherein said storage element is a phase change element.

20. A semiconductor device according to claim 9,

wherein said storage element is a phase change element.

17. A semiconductor device that accesses a memory cell based on a row address and a column address comprising:

a memory array including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction and intersecting with said plurality of word lines, and a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of bit lines;

a plurality of word drivers connected to each of said plurality of word lines;

a column selection circuit connected to said plurality of bit lines and that selects some of said plurality of bit lines to connect to a plurality of read circuits and a plurality of write circuits;

an address hold circuit storing a row address and a column address involved with the previous access cycle; and

an address compare circuit,

wherein said word line is selected by decoding said row address, and said column selection circuit is selected by decoding said column address;

wherein said address compare circuit is a circuit that compares a row address and a column address involved with a current access cycle and said row address and said column address held in said address hold circuit;

wherein each of said memory cells comprises a selection element and a storage element connected in series to corresponding one line of said plurality of bit lines, a control electrode of said selection element is connected to corresponding one line of said plurality of word lines;

wherein said storage element is an element to store data according to variations in resistance;

wherein said word line is not turned on when said address compare circuit detects, in successive read cycles, that both of the row address and column address involved with a current access cycle match the row address and column address involved with the previous access cycle respectively.

18. A semiconductor device according to claim 17, further comprising;

a precharge circuit,

wherein said precharge circuit precharges said bit line to be selected by said column selection circuit, and does not precharge the other bit lines within said memory array.

19. A semiconductor device according to claim 17,

wherein, in successive read access cycles, when said address compare circuit detects that both of the row address and column address involved with a current access cycle match the row address and column address involved with the previous access cycle respectively, said semiconductor device outputs the value of said read circuit.

21-25. -25. (canceled)