Semiconductor device
First Claim
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1. A semiconductor device comprising:
- a power supply terminal;
a plurality of word lines extending in a first direction;
a plurality of bit lines extending in a second direction and intersecting with said plurality of word lines;
a memory array including a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of bit lines;
a plurality of word drivers connected to each of said plurality of word lines;
a plurality of read circuits and write circuits connected to said plurality of bit lines; and
a power supply circuit that converts a power fed to said power supply terminal and supplies said power to internal circuits; and
a detect circuit detecting the variations in power supply potential, wherein each of said plurality of memory cells has a selection element and a storage element alternately connected in series to corresponding one line of said plurality of bit lines, wherein the control electrode of said selection element is connected to corresponding one line of said plurality of word lines, wherein said storage element stores data according to the changes in resistance and allows rewriting the information by flowing electric current, and wherein said selection element is unselected by said word lines, when said circuit for detecting the variations in power supply potential detects variations in power supply potential.
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Abstract
To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.
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Citations
21 Claims
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1. A semiconductor device comprising:
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a power supply terminal;
a plurality of word lines extending in a first direction;
a plurality of bit lines extending in a second direction and intersecting with said plurality of word lines;
a memory array including a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of bit lines;
a plurality of word drivers connected to each of said plurality of word lines;
a plurality of read circuits and write circuits connected to said plurality of bit lines; and
a power supply circuit that converts a power fed to said power supply terminal and supplies said power to internal circuits; and
a detect circuit detecting the variations in power supply potential, wherein each of said plurality of memory cells has a selection element and a storage element alternately connected in series to corresponding one line of said plurality of bit lines, wherein the control electrode of said selection element is connected to corresponding one line of said plurality of word lines, wherein said storage element stores data according to the changes in resistance and allows rewriting the information by flowing electric current, and wherein said selection element is unselected by said word lines, when said circuit for detecting the variations in power supply potential detects variations in power supply potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor device comprising
a power supply terminal; -
a plurality of word lines extending in a first direction;
a plurality of bit lines extending in a second direction and intersecting with said plurality of word lines;
a memory array containing a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of bit lines;
a plurality of word drivers connected to each of said plurality of word lines;
a plurality of read circuits and write circuits connected to said plurality of bit lines;
a power supply circuit converting a power fed to said power supply terminal, and supplying said power to internal circuits; and
a detect circuit detecting the variations in power supply potential, wherein each of said plurality of memory cells has a selection element and a storage element alternately connected in series to corresponding one line of said plurality of bit lines, wherein the control electrode of said selection element is connected to corresponding one line of said plurality of word line, wherein said storage element stores data according to the changes in resistance and allows rewriting the information by flowing electric current, and wherein said bit line and said source line are interconnected to bypass the current to said storage element, when said detect circuit detects a variation in power supply potential. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 20)
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17. A semiconductor device that accesses a memory cell based on a row address and a column address comprising:
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a memory array including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction and intersecting with said plurality of word lines, and a plurality of memory cells disposed at the intersections of said plurality of word lines and said plurality of bit lines;
a plurality of word drivers connected to each of said plurality of word lines;
a column selection circuit connected to said plurality of bit lines and that selects some of said plurality of bit lines to connect to a plurality of read circuits and a plurality of write circuits;
an address hold circuit storing a row address and a column address involved with the previous access cycle; and
an address compare circuit, wherein said word line is selected by decoding said row address, and said column selection circuit is selected by decoding said column address;
wherein said address compare circuit is a circuit that compares a row address and a column address involved with a current access cycle and said row address and said column address held in said address hold circuit;
wherein each of said memory cells comprises a selection element and a storage element connected in series to corresponding one line of said plurality of bit lines, a control electrode of said selection element is connected to corresponding one line of said plurality of word lines;
wherein said storage element is an element to store data according to variations in resistance;
wherein said word line is not turned on when said address compare circuit detects, in successive read cycles, that both of the row address and column address involved with a current access cycle match the row address and column address involved with the previous access cycle respectively. - View Dependent Claims (18, 19)
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21-25. -25. (canceled)
Specification