Method of manufacturing a flexible thin film transistor array panel including plastic substrate

• US 20060148141A1
• Filed: 01/03/2006
• Published: 07/06/2006
• Est. Priority Date: 01/03/2005
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Tae-Young, Seo, Jong-Hyun
• Granted Patent: US 7,507,616 B2
• Time in Patent Office: Days
• US Class Current: 438/151
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

A method of manufacturing a flexible display is provided, which includes forming a gate line including a gate electrode on a substrate, sequentially depositing a gate insulating layer covering the gate line, and a semiconductor layer, firstly etching the semiconductor layer; secondly etching the semiconductor layer, forming a data line including a source electrode, and a drain electrode on the semiconductor layer and the gate insulating layer; and forming a pixel electrode connected to the drain electrode.

Claims

1. A method for manufacturing a flexible display, comprising:

forming a gate line comprising a gate electrode on a substrate;

depositing a gate insulating layer covering the gate line;

depositing a semiconductive layer covering the gate insulating layer;

firstly etching the semiconductor layer;

secondly etching the semiconductor layer;

forming a data line including a source electrode and a drain electrode on the semiconductor layer; and

forming a pixel electrode connected with the drain electrode.

2. The method of claim 1, wherein after firstly etching the semiconductor layer, the semiconductor layer covers the gate electrode.

3. The method of claim 1, wherein the substrate expands when depositing the gate insulating layer and the semiconductor layer and the expanded substrate is restored to an initial size after firstly etching the semiconductor layer.

4. The method of claim 3, wherein after secondly etching the semiconductor layer, the semiconductor layer covers the gate electrode on the restored substrate.

5. The method of claim 1, wherein after firstly and secondly etching the semiconductor layer, the semiconductor layer is an island shape.

6. The method of claim 1, further comprising:

forming a passivation layer before forming the pixel electrode.

7. The method of claim 6, wherein the passivation layer comprises:

a first passivation layer made of an inorganic material; and

a second passivation layer made of an organic material.

8. The method of claim 1, wherein the semiconductor layer comprises an intrinsic amorphous silicon layer and extrinsic amorphous silicon layer.

9. The method of claim 1, wherein the substrate is a plastic substrate.

10. The method of claim 9, wherein the plastic substrate comprises:

a layer made of at least one material selected from a group consisting of polyacrylate, polyethylene-terephthalate, polyethylene-naphthalate, polycarbonate, polyarylate, polyetherimide, polyehtersulfone, and polyimides.

11. The method of claim 1, further comprising:

forming a barrier layer on the substrate.

12. The method of claim 1, further comprising:

forming a color filter below the pixel electrode.

13. The method of claim 1, wherein a photoresist including a plurality of portions having varying thickness is used for secondly etching the semiconductor layer and forming a data line including a source electrode and a drain electrode on the semiconductor layer.

14. The method of claim 13, wherein a portion of the photoresist faces the portion between the source electrode and the drain electrode, and

wherein another portion of the photoresist faces the data line and the drain electrode.