Method of forming gate insulation layers of different characteristics

• US 20060148163A1
• Filed: 08/04/2005
• Published: 07/06/2006
• Est. Priority Date: 12/30/2004
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Reichel, Carsten, Kammler, Thorsten, Wieczorek, Karsten
• Application Number:
  US11/196,881
• Publication Number:
  US 20060148163A1
• Time in Patent Office: Days
• US Class Current: 438/216
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

The present invention describes a method for forming different types of gate insulation layers, wherein the formation of one type of gate insulation layer is highly decoupled from the formation of the other type of gate insulation layer. Thus, in some embodiments, critical oxidation processes may finely be tuned on an individual basis. This is accomplished by providing a mask layer that may substantially prevent any impact on an initially made insulation layer during a subsequent manufacturing process of a second gate insulation layer.

Claims

1. A method, comprising:

forming a first dielectric layer having a first specified characteristic on a first semiconductor region and a second semiconductor region, said first and second semiconductor regions formed on a substrate;

forming a mask layer above said substrate to expose a first portion of said first dielectric layer located above said first semiconductor region and to cover a second portion of said first dielectric layer located above said second semiconductor region;

removing said first portion of said first dielectric layer; and

forming a second dielectric layer with a second specified characteristic on said first semiconductor region, said first characteristic differing from said second characteristic and said mask layer preventing said second dielectric layer from forming on said second portion of said first dielectric layer.

2. The method of claim 1, wherein forming said first dielectric layer comprises exposing said substrate to an oxidizing ambient to oxidize a portion of said first and second semiconductor regions.

3. The method of claim 1, wherein forming said first dielectric layer comprises depositing a first dielectric material.

4. The method of claim 1, further comprising depositing a layer of a first electrode material above said first and second semiconductor regions.

5. The method of claim 4, wherein said layer of a first electrode material has a thickness that is greater than a design height of a first gate electrode to be formed above said first semiconductor region.

6. The method of claim 4, wherein forming said mask layer comprises depositing a layer of a second electrode material.

7. The method of claim 6, wherein a thickness of said layer of a second gate electrode material is greater than a design height of a second gate electrode to be formed above said second semiconductor region.

8. The method of claim 1, wherein forming said second dielectric layer comprises exposing said substrate to an oxidizing ambient.

9. The method of claim 1, wherein forming said second dielectric layer comprises depositing a second dielectric material.

10. The method of claim 6, further comprising removing excess material of said first dielectric layer.

11. The method of claim 10, further comprising planarizing the layer of a first gate electrode material and the mask layer to provide a substantially flat first gate electrode layer above said first semiconductor region and a substantially flat second gate electrode layer above said second semiconductor region.

12. The method of claim 1, wherein said first characteristic represents a first thickness corresponding to a design thickness of an insulation layer of a circuit element to be formed above said second semiconductor region.

13. The method of claim 1, wherein said second characteristic represents a second thickness corresponding to a design thickness of an insulation layer of a circuit element to be formed above said first semiconductor region.

14. The method of claim 1, wherein said first and second characteristics represent a first and a second thickness, respectively, and said second thickness is less than said first thickness.

15. The method of claim 1, wherein said first and second characteristics represent a first and a second thickness, respectively, and said first thickness is less than said second thickness.

16. The method of claim 1, wherein said first and second characteristics represent a first and a second thickness, respectively, and said second thickness is less than approximately 2 nm.

17. The method of claim 1, wherein said first semiconductor region is located in a first die region assigned to a first functional block to be formed and said second semiconductor region is located in a second die region assigned to a second functional block to be formed in said second die region.

18. The method of claim 4, further comprising removing excess material of said first electrode material above said second semiconductor region to expose said mask layer and removing said mask layer.

19. The method of claim 18, further comprising reducing a thickness of said second portion to obtain a value corresponding to a final desired value.

20. The method of claim 19, further comprising depositing a layer of a second electrode material and removing excess material of said layer of a second electrode material to expose said first electrode material formed above said first semiconductor region.

21. The method of claim 1, wherein said first and second characteristics differ in material composition.