Atomic layer deposited hafnium tantalum oxide dielectrics

• US 20060148180A1
• Filed: 01/05/2005
• Published: 07/06/2006
• Est. Priority Date: 01/05/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 7,560,395 B2
• Time in Patent Office: Days
• US Class Current: 438/287
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02318 post-treatment
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31637 Deposition of Tantalum oxides, e.g. Ta2O5
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A dielectric layer containing an atomic layer deposited hafnium tantalum film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. In an embodiment, a hafnium tantalum oxide film is formed by depositing hafnium and tantalum by atomic layer deposition onto a substrate surface. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited hafnium tantalum oxide film, and methods for forming such structures.

Claims

1. A method comprising:

forming a source region and a drain region separated by a body region;

forming a gate; and

forming a dielectric layer above the body region and below the gate, the dielectric layer containing a hafnium tantalum oxide layer, the hafnium tantalum oxide layer formed by atomic layer deposition including;

introducing a precursor containing hafnium to a substrate; and

introducing a precursor containing tantalum to the substrate.

2. The method of claim 1, wherein forming the gate includes forming the gate as a control gate, and forming the dielectric layer includes forming the dielectric layer as an inter-gate dielectric below the control gate and above a floating gate.

3. The method of claim 1, wherein introducing a precursor containing tantalum includes pulsing a tantalum ethoxide precursor.

4. The method of claim 1, wherein introducing a precursor containing hafnium includes pulsing a hafnium nitrate precursor.

5. The method of claim 1, wherein the method includes annealing the dielectric layer after forming the hafnium tantalum oxide layer.

6. The method of claim 1, wherein the method includes conducting a surface nitridation in a nitrogen based ambient before forming the dielectric layer.

7. The method of claim 1, wherein the method is a method of forming an integrated circuit including forming the dielectric layer as a gate insulator of a transistor in the integrated circuit.

8. The method of claim 1, wherein the method is a method of forming an integrated circuit including forming the dielectric layer as a gate insulator in a CMOS transistor in the integrated circuit.

9. The method of claim 1, wherein forming the dielectric layer includes forming the dielectric layer as a nanolaminate having the hafnium tantalum oxide layer.

10. The method of claim 9, wherein forming the dielectric layer includes forming a tantalum oxide layer as a layer of the nanolaminate.

11. The method of claim 9, wherein forming the dielectric layer includes forming a hafnium oxide layer as a layer of the nanolaminate.

12. The method of claim 1, wherein the method is a method of forming an integrated circuit on a silicon-on-insulator substrate.

13. The method of claim 1, wherein the method includes forming a capacitor containing a second hafnium tantalum oxide layer and forming the second hafnium tantalum oxide layer by atomic layer deposition.

14. The method of claim 13, wherein forming a capacitor containing a second hafnium tantalum oxide layer includes forming the second hafnium tantalum oxide layer of the capacitor in an analog integrated circuit.

15. The method of claim 13, wherein forming a capacitor containing a second hafnium tantalum oxide layer includes forming the second hafnium tantalum oxide layer of the capacitor in a radio frequency integrated circuit.

16. The method of claim 13, wherein forming a capacitor containing a second hafnium tantalum oxide layer includes forming the second hafnium tantalum oxide layer of the capacitor in a mixed signal integrated circuit.

17. The method of claim 1, wherein the method is a method of forming a memory device.

18. The method of claim 1, wherein the method is a method of forming an electronic system.

19. A method comprising:

forming a memory array in a substrate including;

forming a source region and a drain region separated by a body region;

forming a gate; and

forming a dielectric layer above the body region and below the gate, the dielectric layer containing a hafnium tantalum oxide layer, the hafnium tantalum oxide layer formed by atomic layer deposition including;

introducing a precursor containing hafnium to the substrate; and

introducing a precursor containing tantalum to the substrate; and

forming a connection to couple the memory array to a bus.

20. The method of claim 19, wherein forming the gate includes forming the gate as a control gate, and forming the dielectric layer includes forming the dielectric layer as an inter-gate dielectric below the control gate and above a floating gate.

21. The method of claim 19, wherein pulsing a precursor containing hafnium includes a hafnium halide precursor.

22. The method of claim 19, wherein pulsing a precursor containing tantalum includes pulsing tantalum halide precursor.

23. The method of claim 19, wherein pulsing a precursor containing tantalum includes pulsing a tantalum ethoxide precursor.

24. The method of claim 19, wherein the method is a method of forming a memory device including forming the dielectric layer as a gate insulator of a transistor in the memory device.

25. The method of claim 19, wherein the method is a method of forming a flash memory device including forming a second hafnium tantalum oxide layer by atomic layer deposition, the second hafnium tantalum oxide layer formed as part of an inter-gate insulator of a floating gate transistor in the flash memory device.

26. The method of claim 19, wherein the method is a method of forming a memory device including forming a second hafnium tantalum oxide layer by atomic layer deposition, the second hafnium tantalum oxide layer formed as part of a capacitor in the memory device.

27. The method of claim 19, wherein the method includes forming a dynamic random access memory.

28. A method comprising:

providing a controller;

coupling an integrated circuit to the controller, wherein at least one of the integrated circuit or the controller includes a dielectric layer above a body region and below a gate, the body region separating a source region and a drain region, the dielectric layer containing a hafnium tantalum oxide layer, the hafnium tantalum oxide layer formed by atomic layer deposition including;

pulsing a precursor containing tantalum onto a substrate; and

pulsing a precursor containing hafnium onto the substrate.

29. The method of claim 28, wherein forming the gate includes forming the gate as a control gate and forming the dielectric layer includes forming the dielectric layer as an inter-gate dielectric below the control gate and above a floating gate.

30. The method of claim 28, wherein pulsing a precursor containing hafnium includes pulsing a hafnium nitrate precursor.

31. The method of claim 28, wherein pulsing a precursor containing tantalum includes pulsing at least one of a tantalum ethoxide precursor or a tantalum halide precursor.

32. The method of claim 28, wherein coupling an integrated circuit to the controller includes coupling a memory device as the integrated circuit.

33. The method of claim 28, wherein forming the hafnium tantalum oxide layer includes forming the hafnium tantalum oxide layer as a layer in the dielectric layer formed as a nanolaminate.

34. The method of claim 28, wherein forming the hafnium tantalum oxide layer includes forming the hafnium tantalum oxide layer as a layer in the dielectric layer formed as a nanolaminate having a tantalum oxide layer.

35. The method of claim 28, wherein forming the hafnium tantalum oxide layer includes forming the hafnium tantalum oxide layer as a layer in the dielectric layer formed as a nanolaminate having a hafnium oxide layer.

36. The method of claim 28, wherein providing a controller includes providing a processor.

37. The method of claim 28, wherein coupling an integrated circuit to the controller includes coupling a mixed signal integrated circuit as the integrated circuit.

38. The method of claim 28, wherein the method is a method of forming an information handling system.

39. An electronic device comprising:

a substrate;

a source region and a drain region separated by a body region;

a dielectric layer above the body region, the dielectric layer having an atomic layer deposited hafnium tantalum oxide layer; and

a gate above the dielectric layer.

40. The electronic device of claim 39, wherein the gate is a control gate and the dielectric layer is an inter-gate dielectric disposed between the control gate and a floating gate.

41. The electronic device of claim 39, wherein the electron device includes a memory.

42. The electronic device of claim 41, wherein the dielectric layer is a gate insulator of a transistor in a memory array of the memory.

43. The electronic device of claim 41, wherein the electronic device includes a second dielectric layer having a hafnium tantalum oxide layer as a dielectric of a capacitor in the memory.

44. The electronic device of claim 41, wherein the memory includes a flash memory device.

45. The electronic device of claim 44, wherein the dielectric layer is an inter-gate insulator between the gate configured as a control gate and a floating gate of a transistor in the flash memory device.

46. The electronic device of claim 44, wherein the dielectric layer is a gate insulator between the gate configured as a floating gate and the body region configured as a channel of a transistor in the flash memory device.

47. A system comprising:

a controller;

an integrated circuit coupled to the controller, wherein at least one of the controller or integrated circuit includes;

a substrate;

a source region and a drain region separated by a body region in the substrate;

a dielectric layer above the body region, the dielectric layer having an atomic layer deposited hafnium tantalum oxide layer; and

a gate above the dielectric layer.

48. The system of claim 47, wherein the gate is a control gate and the dielectric layer is an inter-gate dielectric disposed between the control gate and a floating gate.

49. The system of claim 47, wherein the body region has a nitrated surface onto which the dielectric layer is disposed.

50. The system of claim 47, wherein the integrated circuit includes a memory.

51. The system of claim 47, wherein the controller includes a processor.

52. The system of claim 47, wherein the integrated circuit includes a mixed signal integrated circuit.

53. The system of claim 47, wherein the system is an information handling system.