Semiconductor integrated circuit device and wireless communication system

• US 20060148416A1
• Filed: 01/04/2006
• Published: 07/06/2006
• Est. Priority Date: 01/05/2005
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kasahara, Masumi, Harasawa, Yoshiaki
• Application Number:
  US11/324,277
• Publication Number:
  US 20060148416A1
• Time in Patent Office: Days
• US Class Current: 455/71
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The present invention supplies a stable power supply voltage from small output currents to large output currents, regardless of operation states of a semiconductor integrated circuit device. When an output current of the regulator is small (idle mode), all switches go off. Thereby, power is supplied to a transistor via resistors, a load of a transistor becomes large, and current consumption of the regulator can be reduced. Since a transistor goes off, parasitic capacitance can be reduced, and a sufficient phase margin can be ensured between output of a differential voltage comparator and an output signal of the regulator. In normal operation, all the switches go on, load resistance is reduced to reduce noise, and driving capability is improved to supply stable power supply voltages.

Claims

1. A semiconductor integrated circuit device, comprising:

a receiving block;

a transmitting block; and

a first power supply unit that supplies a power supply voltage to the receiving block and the transmitting block, respectively,

wherein the first power supply unit includes a load element control unit that makes load resistance of the first power supply unit to be higher than the time when the receiving block and the transmitting block are operating normally, in idle mode in which functions of the receiving block and the transmitting block are inactive.

2. The semiconductor integrated circuit device according to claim 1,

wherein the first power supply unit includes an electrostatic capacity control unit that arbitrarily makes electrostatic capacity values for phase compensation variable, and

wherein when the receiving block and the transmitting block are in idle mode, the electrostatic capacity control unit makes electrostatic capacity values for phase compensation smaller than the time when the receiving block and the transmitting block are operating normally.

3. The semiconductor integrated circuit device according to claim 2,

wherein electrostatic capacity values for phase compensation made variable by the electrostatic capacity control unit are parasitic capacitance values of a final-stage output transistor, and

wherein the electrostatic capacity control unit makes electrostatic capacity values for phase compensation variable by switching the number of connections of at least two final-stage output transistors.

4. The semiconductor integrated circuit device according to claim 1, including a temperature detecting means that detects an internal temperature of the semiconductor integrated circuit device,

wherein the first power supply unit supplies a power supply voltage to the temperature detecting means.

6. The semiconductor integrated circuit device according to claim 1, including a third power supply unit that supplies a power supply voltage to a front end module externally connected to the semiconductor integrated circuit device,

wherein the third power supply unit includes a load element control unit that makes load resistance of the third power supply unit higher than the time when the receiving block and the transmitting block are operating normally when the receiving block and the transmitting block are in idle mode.

5. A semiconductor integrated circuit device, comprising:

an oscillator block comprising circuits common to a receiving block and a transmitting block; and

a second power supply unit that supplies a power supply voltage to the oscillator block,

wherein the second power supply unit includes a load element control unit that makes load resistance of the second power supply unit higher than the time when the receiving block and the transmitting block are operating normally, in idle mode in which functions of the receiving block and the transmitting block are inactive.

7. A wireless communication system including a semiconductor integrated circuit device for radio frequency processing that demodulates a receive signal and modulates a transmission signal,

wherein the semiconductor integrated circuit device comprises:

a receiving block;

a transmitting block; and

a first power supply unit that supplies a power supply voltage to the receiving block and the transmitting block, respectively,

wherein the first power supply unit includes a load element control unit that makes load resistance of the first power supply unit higher than the time when the receiving block and the transmitting block are operating normally, in idle mode in which functions of the receiving block and the transmitting block are inactive.

8. The wireless communication system according to claim 7,

wherein the first power supply unit includes an electrostatic capacity control unit that arbitrarily makes electrostatic capacity values for phase compensation variable, and

wherein when the receiving block and the transmitting block are in idle mode, the electrostatic capacity control unit makes electrostatic capacity values for phase compensation smaller than the time when the receiving block and the transmitting block are operating normally.

9. The wireless communication system according to claim 8,

wherein electrostatic capacity values for phase compensation made variable by the electrostatic capacity control unit are parasitic capacitance values of a final-stage output transistor, and

wherein the electrostatic capacity control unit makes electrostatic capacity values for phase compensation variable by switching the number of connections of at least two final-stage output transistors.

10. The wireless communication system according to claim 7, including a temperature detecting means that detects an internal temperature of the semiconductor integrated circuit device,

wherein the first power supply unit supplies a power supply voltage to the temperature detecting means.

12. The wireless communication system according to claim 7, including a front end module externally connected to the semiconductor integrated circuit device,

wherein the semiconductor integrated circuit device includes a third power supply unit that supplies a power supply voltage to the front end module, and

wherein the third power supply unit includes a load element control unit that makes load resistance of the third power supply unit higher than the time when the receiving block and the transmitting block are operating normally when the receiving block and the transmitting block are in idle mode.

11. A wireless communication system, comprising:

an oscillator block comprising circuits common to a receiving block and a transmitting block; and

a second power supply unit that supplies a power supply voltage to the oscillator block,

wherein the second power supply unit includes a load element control unit that makes load resistance of the second power supply unit higher than the time when the receiving block and the transmitting block are operating normally, in idle mode in which functions of the receiving block and the transmitting block are inactive.