Method and system for calibrating a light emitting device display

• US 20060149493A1
• Filed: 12/01/2005
• Published: 07/06/2006
• Est. Priority Date: 12/01/2004
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Sambandan, Sanjiv, Servati, Peyman, Nathan, Arokia
• Granted Patent: US 8,314,783 B2
• Time in Patent Office: Days
• US Class Current: 702/118
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/029 by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Abstract

A method and system for calibrating a light emitting device display is provided. The display includes a plurality of pixel circuits, each having a light emitting device. The system for the calibration monitors current drawn from a row of the display array, and generates a correction parameter to correct brightness level of the light emitting device.

Claims

1. A system for calibration of a display array having a plurality of pixel circuits, comprising:

an error extraction system for extracting error including;

a first module for monitoring a row current in a row of the display array;

a second module for generating a reference current; and

a third module for obtaining an error between the row current and the reference current, and

an error estimation system for estimating a correction parameter based on the error to adjust a data voltage applied to the display array.

2. A system according to claim 1, further comprising a dummy row corresponding to a row of the display array and having a plurality of the pixel circuits, for providing the reference current.

3. A system according to claim 2, wherein the pixel circuits in the dummy row receive data voltages from a data driver, which are identical to those of the pixel circuits in the row of the display array, and wherein the second module monitors a current drawn from the pixel circuits in the dummy row to provide the reference current.

4. A system according to claim 3 further comprising a system for controlling and scheduling a normal display operation and a calibration to the display array, and wherein the controlling and scheduling system selects a row of the display array so as to separately implement the calibration to the rows of the display array.

5. A system according to claim 4, further comprising a first switch system for connecting the rows of the display array to a main voltage supply, a second switch system for selectively connecting a row of the display array to the error estimation system, and a third switch system for connecting the dummy row to the data driver, and wherein the controlling and scheduling system manages the operations of the first, second and third switch systems.

6. A system according to claim 5, wherein during the calibration, the rows of the display array are sequentially connected to the error extraction system through the second switch system, and the dummy row is connected to the data driver through the third switch system.

7. A system according to claim 6, wherein during the calibration, the first module monitors the row current in the selected row of the display array, and the third module compares each monitored row current to the reference current.

8. A system according to claim 5, wherein during the normal display operation, the rows of the display array are connected to the main voltage supply through the first switch system, and the dummy row is disconnected from the data driver.

9. A system according to claim 1, wherein the error estimation system includes a look up table for storing a plurality of correction parameters, and the error estimation system retrieves a corresponding correction parameter for the row of the display array from the look up table based on the error.

10. A system according to claim 9, wherein the error estimation system retrieves the corresponding correction parameter for the row of the display array from the look up table based on the error and a total data voltage applied to the pixel circuits in the row of the display array.

11. A system according to claim 10, wherein the average of the correction parameters for all rows of the display array is applied to data voltages for all of the pixel circuits in the display array.

12. A system according to claim 10, wherein the look up table includes a mapping parameter specific to the total data voltage and the transfer function of the third module.

13. A system according to claim 1, wherein the error estimation system includes a calculation module for calculating a corresponding correction parameter for the row of the display array based on the error.

14. A system according to claim 13, wherein the calculation module calculates the corresponding correction parameter for the row of the display array based on the error and a total data voltage applied to the pixel circuits in the row of the display array.

15. A system according to claim 14, wherein the average of the correction parameters for all rows of the display array is applied to data voltages for all of the pixel circuits in the display array.

16. A system according to claim 1, wherein at least one of the first and second modules includes a current mirror.

17. A system according to claim 1, wherein the pixel circuit includes a light emitting device and a driver transistor connected to the light emitting device, the light emitting device or the driver transistor being connected to a voltage supply in a corresponding row of the display array, and the first module monitoring the row current drawn from the voltage supply.

18. A system according to claim 1, wherein the pixel circuit is a voltage programmed pixel circuit.

19. A system according to claim 1, wherein the display array is an AMOLED display array.

20. A system according to claim 1, wherein the display array has a-Si, polysilicon, or crystalline based backplane.

21. A system according to claim 1, wherein the pixel circuit has n-type transistors.

22. A system according to claim 1, wherein the pixel circuit has p-type transistors.

23. A method of calibration of a display array having a plurality of pixel circuits, comprising the steps of:

extracting error, including;

providing a reference current;

monitoring a row current in a row of the display array; and

for the row, obtaining an error between the row current and the reference current,

estimating a correction parameter for the row based on the error and a total data voltages applied to the pixel circuits in the row of the display array.

24. A method according to claim 23, further comprising the steps of:

selecting a next row of the display array and repeating the steps of extracting error and estimating the correction parameter, and

calculating an average of the correction parameters for the rows of the display array to apply the average of the correction parameters to data voltages applied to the display array.

25. A method according to claim 24, further comprising the step of applying the average of the correction parameters to data voltages for the pixel circuits in the display array.

26. A method according to claim 23, wherein the step of providing a reference current includes the step of:

connecting a dummy row corresponding to a row of the display array to a data driver generating the data voltages; and

monitoring a current drawn from the dummy row to provide the reference current.