Semiconductor device having a mode of functional test
First Claim
1. A semiconductor device having an access time validity test mode, comprising:
- a circuit block to which an input signal is input at a timing in accordance with an input clock, and which outputs an output signal having a value corresponding to said input signal;
a first signal path for guiding a test input signal, which has been supplied to a first pad, to a signal input terminal of said circuit block;
a second signal path for guiding a test clock, which has been supplied to a second pad, to a clock input terminal of said circuit block;
a third signal path for guiding a test output signal, which has been output from a signal output terminal of said circuit block, to a third pad via a dummy latch; and
a fourth signal path for guiding the test output signal, which has been output from the signal output terminal of said circuit block, to a fourth pad, wherein the dummy latch is constituted so as to latch the test output signal at substantially a same operating speed as an operational latch for latching an output signal of said circuit block during a normal operation, and wherein said third signal path is formed so that a wiring delay time from the signal output terminal of said circuit block to the dummy latch is substantially equal to a wiring delay time from the signal output terminal of said circuit block to the operational latch.
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Accused Products
Abstract
A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a clock input terminal of the circuit block; a third signal path for guiding a test output signal from a output terminal of the circuit block to a pad via a dummy latch; and a fourth signal path for guiding the test output signal from the output terminal of the circuit block, to another pad. A dummy latch latches the test output signal at substantially a same speed as an operational latch during a normal operation. The third signal path has a wiring delay time from the output terminal to the dummy latch that is substantially equal to a wiring delay time from the output terminal to the operational latch.
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Citations
10 Claims
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1. A semiconductor device having an access time validity test mode, comprising:
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a circuit block to which an input signal is input at a timing in accordance with an input clock, and which outputs an output signal having a value corresponding to said input signal;
a first signal path for guiding a test input signal, which has been supplied to a first pad, to a signal input terminal of said circuit block;
a second signal path for guiding a test clock, which has been supplied to a second pad, to a clock input terminal of said circuit block;
a third signal path for guiding a test output signal, which has been output from a signal output terminal of said circuit block, to a third pad via a dummy latch; and
a fourth signal path for guiding the test output signal, which has been output from the signal output terminal of said circuit block, to a fourth pad, wherein the dummy latch is constituted so as to latch the test output signal at substantially a same operating speed as an operational latch for latching an output signal of said circuit block during a normal operation, and wherein said third signal path is formed so that a wiring delay time from the signal output terminal of said circuit block to the dummy latch is substantially equal to a wiring delay time from the signal output terminal of said circuit block to the operational latch. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device having an access time measuring test mode, comprising:
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a circuit block to which an input signal is input at a timing in accordance with an input clock, and which outputs an output signal having a value corresponding to the input signal;
an operational path for latching the output signal of said circuit block during a normal operation;
a dummy latch for latching the output signal of said circuit block during a test operation;
a first signal path for guiding a test input signal, which has been supplied to a first pad, to a signal input terminal of said circuit block;
a second signal path for guiding a test clock, which has been supplied to a second pad, to a clock input terminal of said circuit block;
a third signal path for guiding the output signal from a signal output terminal of said circuit block to an input terminal of said operational latch;
a fourth signal path for guiding the output signal from the signal output terminal of said circuit block to an input terminal of said dummy latch, a fifth signal path for guiding a latched signal output from a signal terminal of said dummy latch to a third pad; and
a sixth signal path for guiding the output signal from the signal output terminal of said circuit block to a fourth pad, wherein said dummy latch is constituted so that an access time from when said dummy latch has the output signal of said circuit block input thereto to when said dummy latch outputs the latched signal, is substantially equal to an access time of said operational latch, and wherein said third and fourth signal paths are formed so that a wiring delay time from the signal output terminal of said circuit block to the input terminal of said dummy latch is substantially equal to a wiring delay time from the signal output terminal of said circuit block to the input terminal of said operational latch. - View Dependent Claims (7, 8, 9, 10)
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Specification