Clock simulation system and method
First Claim
1. A method of simulating a digital circuit operating with one or more clock signals, a clock signal being a signal having one or more attributes that provide for determining the time of the next clock signal driven event, the method comprising:
- forming a hardware model representing the circuit;
scheduling one or more time-scheduled events according to the model, the scheduling in a time-scheduled event data structure, a time-scheduled event being an event whose occurrence time in a simulation time frame is defined by reference to a simulation time;
scheduling one or more clock-scheduled events according to the model, a clock-scheduled event being an event whose occurrence time is defined relative to one or more attributes of at least one clock signal in the circuit;
predicting the occurrence time of the clock-scheduled events; and
at any particular simulation time, processing the time-scheduled events for the particular simulation time and clock-scheduled events predicted to occur at the particular simulation time;
such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure.
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Accused Products
Abstract
A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock attributes. The method includes maintaining a data structure for time-scheduled events scheduled to occur at particular simulation-times; and maintaining a data structure for clock-scheduled events each corresponding to a particular clock signal and scheduled to occur at a time that can be determined from at least one attribute of the clock signal, such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure.
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Citations
43 Claims
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1. A method of simulating a digital circuit operating with one or more clock signals, a clock signal being a signal having one or more attributes that provide for determining the time of the next clock signal driven event, the method comprising:
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forming a hardware model representing the circuit;
scheduling one or more time-scheduled events according to the model, the scheduling in a time-scheduled event data structure, a time-scheduled event being an event whose occurrence time in a simulation time frame is defined by reference to a simulation time;
scheduling one or more clock-scheduled events according to the model, a clock-scheduled event being an event whose occurrence time is defined relative to one or more attributes of at least one clock signal in the circuit;
predicting the occurrence time of the clock-scheduled events; and
at any particular simulation time, processing the time-scheduled events for the particular simulation time and clock-scheduled events predicted to occur at the particular simulation time;
such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A carrier medium carrying computer readable code to cause a processor of a processing system to implement a hardware simulator, comprising:
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a hardware model constructed from a description of a digital circuit, the digital circuit including a clock signal;
a time-scheduled event data structure for scheduling time-scheduled events, a time-scheduled event being an event whose occurrence time in a simulation time frame is defined by reference to a simulation time;
a clock-scheduled event data structure for scheduling clock-scheduled events, a clock-scheduled event being an event whose occurrence time is defined relative to one or more attributes of a referenced clock signal; and
an event scheduler arranged to schedule one or more time-scheduled events in the time-scheduled event data structure according to the model, and to schedule one or more clock-scheduled events according to the model, the hardware simulator being arranged, when simulating the hardware model, to predict the simulation time of the clock-scheduled events and at any particular simulation time, process the time-scheduled events for the particular simulation time and clock-scheduled events predicted to occur at the particular simulation time, such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure. - View Dependent Claims (10, 11, 12, 13)
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14. A method of simulating a digital circuit, the circuit including one or more elements and at least one clock signal, each clock signal having one or more attributes, including the clock signal'"'"'s period in units of a simulation-time, the method comprising:
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maintaining a data structure for time-scheduled events, each time-scheduled event scheduled to occur at a particular simulation-time; and
maintaining a data structure for clock-scheduled events, each clock-scheduled event corresponding to a particular clock signal and scheduled to occur at a time that can be determined from one or more attributes of the clock signal, such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure. - View Dependent Claims (15)
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16. A carrier medium carrying computer readable code to instruct a processor to implement a method of simulating a digital circuit comprising:
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accepting code generated from a hardware model of a digital circuit defined in a language, the digital circuit operating according to a clock signal having one or more attributes, the attributes including at least one of the set consisting of the value of the clock period at the current simulation time, an indication of whether or not the clock signal is stopped, an indication of the number of ticks of the clock signal since a reference point in time, the simulation-time corresponding to the reference point, and the simulation-time increment from the present simulation-time to the next tick of the clock signal, a tick being a significant edge of the clock signal; and
running a hardware simulator operating according to the hardware model, the simulator including a scheduler arranged to be able to (a) schedule a clock-scheduled event at a first simulation-time in the future determinable from one or more provided parameters of the clock signal; and
(b) schedule a time-scheduled event at a second simulation-time in the future defined by a provided or determined value of simulation time or simulation time delay;
wherein the simulator is arranged to process the scheduled events, the method such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A method of simulating a digital circuit, the method including the steps of:
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(a) providing a simulated clock signal simulating a digital clock signal having periodic significant transitions, and having one or more attributes;
(b) scheduling one or more clock-scheduled events to occur according to the circuit and one or more values of corresponding attributes of the clock signal in the circuit, a clock-scheduled event being an event whose occurrence time is defined relative to the one or more attributes of the clock signal in the circuit; and
(c) for a scheduled clock-based event, determining the next simulation time in the future for the clock-scheduled event to occur from one or more provided or determined properties of the clock signal, and scheduling the event to occur at the determined simulation time. - View Dependent Claims (30, 31)
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32. A method of simulating a clocked digital circuit, the method including the steps of:
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(a) providing a set of primitives accessible from a hardware description language, the primitives used with a hardware description language definition of the circuit for simulating clocked events occurring at a simulation time in the future defined according to predetermined values for one or more attributes of a clock signal; and
(b) simulating the clocked circuit using the primitives, such that each transition of the clock signal does not need to be scheduled. - View Dependent Claims (33, 34, 35)
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36. A means for simulating a digital circuit operating with one or more clock signals, a clock signal being a signal having one or more attributes that provide for determining the time of the next clock signal driven event, the simulating means comprising:
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means for accepting a hardware model representing the circuit;
means for scheduling one or more time-scheduled events according to the model, the scheduling in a time-scheduled event data structure, a time-scheduled event being an event whose occurrence time in a simulation time frame is defined by reference to a simulation time; and
means for scheduling one or more clock-scheduled events according to the model, a clock-scheduled event being an event whose occurrence time is defined relative to one or more attributes of at least one clock signal in the circuit;
means for predicting the occurrence time of the clock-scheduled events; and
means for processing events, the processing means at any particular simulation time processing the time-scheduled events for the particular simulation time and clock-scheduled events predicted to occur at the particular simulation time, such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43)
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Specification