Multiply-sum dot product instruction with mask and splat

• US 20060149804A1
• Filed: 11/30/2004
• Published: 07/06/2006
• Est. Priority Date: 11/30/2004
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luick, David A., Mejdrich, Eric O.
• Application Number:
  US11/000,437
• Publication Number:
  US 20060149804A1
• Time in Patent Office: Days
• US Class Current: 708/626
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

An instruction, corresponding methods, and circuitry for efficiently performing partial dot sum products are provided. The instruction may include a source select field for specifying one or more source word elements to participate in the dot sum operation. The instruction may also include a target select field for specifying one or more (or none) target word elements for storing the result of the dot sum operation.

Claims

1. A method of generating a dot product sum, comprising:

receiving an instruction specifying at least two source registers and a target register;

generating a dot product sum by multiplying word elements contained in each source register and summing the products of the multiplication, wherein the word elements that participate in the multiplication are specified by one or more bits in the instruction; and

storing the dot product sum in none, one, or more word elements contained in the target register.

2. The method of claim 1, wherein storing the dot product sum comprises storing the dot product sum in none, one, or more word elements, as specified by one or more bits in the instruction.

3. The method of claim 1, wherein the instruction comprises:

a first bit field for specifying source word elements to participate in the dot product sum; and

a second bit field for specifying none or more target word elements for storing the dot product sum.

4. The method of claim 1, wherein each word element contains a floating point number.

5. The method of claim 4, wherein generating the dot product sum comprises masking one or more word elements that do not participate in the multiplication, as specified by one or more bits in the instruction, by replacing those word elements with floating point zero values.

6. The method of claim 1, wherein storing the dot product sum in none, one, or more word elements contained in the target register comprises storing the dot product sum in all word elements contained in the target register, if specified by one or more bits contained in the instruction.

7. The method of claim 1, wherein the one or more bits are contained in a field separate from an opcode field.

8. A method of generating a dot product sum with accumulate, comprising:

receiving an instruction specifying at least two source registers and a target register;

generating a dot product sum by multiplying word elements contained in each source register and summing the products of the multiplication, wherein the word elements that participate in the multiplication are specified by one or more bits in the instruction;

adding the dot product sum to a value contained in an accumulate register to generate an accumulated sum; and

storing the accumulated sum in none, one, or more word elements contained in the target register.

9. The method of claim 8, further comprising:

storing the accumulated sum in the accumulate register, only if specified by one or more bits contained in the instruction.

10. The method of claim 8, wherein storing the accumulated sum comprises storing the accumulated sum in none, one, or more word elements, as specified by one or more bits in the instruction.

11. The method of claim 10, wherein the instruction comprises:

a first bit field for specifying source word elements to participate in the dot product sum; and

a second bit field for specifying none or more target word elements for storing the accumulated sum.

12. A circuit for executing a dot product sum instruction, comprising:

mask logic configured to select word elements from at least two source registers to participate in a calculation of a dot product sum based on one or more bits contained in the instruction;

multiply sum logic configured to perform the calculation of the dot product sum based on the word elements selected by the mask logic; and

target routing logic configured to store the dot product sum calculated by the multiply sum logic in none, one, or all word elements of a target register.

13. The circuit of claim 12, wherein the target routing logic is configured to store the dot product sum in none, one, or more word elements, as specified by one or more bits in the instruction.

14. The circuit of claim 12, wherein the instruction comprises:

a first bit field for specifying source word elements to participate in the dot product sum; and

a second bit field for specifying none or more target word elements for storing the dot product sum.

15. The circuit of claim 12, wherein each word element contains a floating point number.

16. The circuit of claim 15, wherein the masking logic is configured to mask one or more word elements that do not participate in the multiplication, as specified by one or more bits in the instruction, by replacing those word elements with floating point zero values.

17. The circuit of claim 12, wherein the routing logic is configured to store the dot product sum in all word elements contained in the target register, if specified by one or more bits contained in the instruction.

18. A circuit for executing a dot product sum with accumulate instruction, comprising:

mask logic configured to select word elements from at least two source registers to participate in a calculation of a dot product sum based on one or more bits contained in the instruction;

multiply-sum-accumulate logic configured to perform the calculation of the dot product sum based on the word elements selected by the mask logic and add the dot product sum to the contents of an accumulate register to generate an accumulated sum; and

target routing logic configured to store the accumulated sum in none, one, or all word elements of a target register.

19. The circuit of claim 18, wherein the target routing logic is configured to store the accumulated sum in the accumulate register, only if specified by one or more bits contained in the instruction.

20. The circuit of claim 18, the target routing logic is configured to store the accumulated sum in none, one, or more word elements, as specified by one or more bits in the instruction.

21. The method of claim 20, wherein the instruction comprises:

a first bit field for specifying source word elements to participate in the dot product sum; and

a second bit field for specifying none or more target word elements for storing the accumulated sum.