Bus controller and bus control method for use in computer system

• US 20060149886A1
• Filed: 01/05/2006
• Published: 07/06/2006
• Est. Priority Date: 01/05/2005
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Wei, Jui-Ming, Chen, Lin-Hung
• Granted Patent: US 7,353,315 B2
• Time in Patent Office: Days
• US Class Current: 710/311
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A bus controller and a control method are used in a computer system. In a bus controller, a bus controller main circuit issues a first signal to the central processing unit in response to a bus configuration cycle for announcing a first-level bus that the first group of components is coupled to. A virtual bridge device issues a second signal to the central processing unit in response to the bus configuration cycle for announcing a second-level bus that the second group of components is coupled to. A path selection unit electrically connected to the first and second groups of components via the first-level and second-level buses, respectively, outputs a normal device select signal to one of the first-level and second-level buses while outputting an invalid device select signal to the other of the first-level and second-level buses according to address data of a transaction.

Claims

1. A bus controller of a computer system for communicating a central processing unit with a first group of components and a second group of components, comprising:

a bus controller main circuit in communication with the central processing unit, issuing a first signal to the central processing unit in response to a bus configuration cycle for announcing a first-level bus that the first group of components is coupled to; and

a virtual bridge device in communication with the central processing unit, issuing a second signal to the central processing unit in response to said bus configuration cycle for announcing a second-level bus that the second group of components is coupled to.

2. The bus controller according to claim 1 further comprising:

a path selection unit electrically connected to the first group of components and the second group of components via said first-level bus and said second-level bus respectively.

3. The bus controller according to claim 2 wherein the path selection unit outputs a normal device select signal to a specified one of said first-level bus and said second-level bus while outputting an invalid device select signal to the other of said first-level bus and said second-level bus in response to a transaction directed to said specified one of said first-level bus and said second-level bus.

4. The bus controller according to claim 1 wherein the operating system of the computer has the central processing unit assert said bus configuration cycle to said bus controller main circuit and said virtual bridge device while the computer system is initialized.

5. The bus controller according to claim 1 wherein said transaction is directed to the first-level bus when a bus code carried by said transaction is in a first value, and said transaction is directed to the second-level bus when a bus code carried by said transaction is in a second value.

6. The bus controller according to claim 3 wherein said transaction further carries a device code, and said normal device select signal corresponds to said device code while said invalid device select signal corresponds to a change to said device code.

7. The bus controller according to claim 6 wherein said invalid device select signal includes a plurality of zeroed bits to correspond to said device code.

8. The bus controller according to claim 1 wherein said first-level bus is closer to the central processing unit than said second-level bus.

9. The bus controller according to claim 1 wherein said virtual bridge device is implemented with a set of registers storing therein configuration header data of a physical PCI-to-PCI bridge device.

10. The bus controller according to claim 1 wherein the first group of components comprises at least one internal component selected from a group consisting of an AC97 audio chip, a serial ATA control chip and a USB control chip.

11. The bus controller according to claim 1 wherein the second group of components comprises at least one external PCI device.

12. A bus controller of a computer system for communicating a central processing unit with a first group of components and a second group of components, comprising:

a bus controller main circuit electrically connected to the central processing unit;

a virtual bridge device electrically connected to the central processing unit via said bus controller main circuit and electrically connected to said bus controller main circuit via an internal line; and

a path selection unit electrically connected to said bus controller main circuit and communicable with the first group of components and the second group of components via a bus device, said path selection unit transferring a transaction to the first group of components via said bus device when a bus code carried by said transaction has a first value and transferring said transaction to the second group of components via said bus device when said bus code carried by said transaction has a second value.

13. The bus controller according to claim 12 wherein said bus device includes a first bus and a second bus that are announced as an upper-level bus that the first group of components is coupled to and a lower-level bus that the second group of components is coupled to by said bus controller main circuit and said virtual bridge device, respectively, in response to a bus configuration cycle asserted by the operating system via the central processing unit.

14. The bus controller according to claim 13 wherein the first group of components comprises at least one internal component selected from a group consisting of an AC97 audio chip, a serial ATA control chip and a USB control chip and the second group of components comprises at least one external PCI device.

15. The bus controller according to claim 13 wherein said path selection unit electrically connected among said bus controller main circuit, said upper-level bus and second lower-level bus.

16. The bus controller according to claim 15 wherein said path selection unit outputs a normal device select signal to said upper-level bus while outputting an invalid device select signal to said lower-level bus when said bus code has said first value, and said path selection unit outputs a normal device select signal to said lower-level bus while outputting an invalid device select signal to said upper-level bus when said bus code has said second value.

17. The bus controller according to claim 16 wherein said transaction further carries a device code, and said normal device select signal corresponds to said device code while said invalid device select signal corresponds to a change to said device code.

18. The bus controller according to claim 17 wherein said invalid device select signal includes a plurality of bits corresponding to said device code, which are zeroed.

19. The bus controller according to claim 12 wherein said virtual bridge device is implemented with a set of registers storing therein configuration header data of a physical PCI-to-PCI bridge device.

20. A bus control method for use in a computer system, the computer system comprising a central processing unit, a bus controller main circuit, a virtual bridge device, a first group of components, and a second group of components, the bus control method comprising:

the bus controller main circuit announcing a first-level bus that the first group of components is coupled to;

the virtual bridge device announcing a second-level bus that the second group of components is coupled to in response to a bus configuration cycle asserted when the computer system is initialized;

outputting a normal select signal to said first-level bus when the address data of a transaction received by the bus controller main circuit indicates a bus code of said first-level bus; and

outputting a normal select signal to said second-level bus when the address data of a transaction received by the bus controller main circuit indicates a bus code of said second-level bus.

21. The method according to claim 20 further comprising:

outputting an invalid select signal to said first-level bus when the address data of a transaction received by the bus controller main circuit indicates a bus code of said second-level bus; and

outputting an invalid select signal to said second-level bus when the address data of a transaction received by the bus controller main circuit indicates a bus code of said first-level bus.

22. The method according to claim 20 wherein said virtual bridge device is implemented with a set of registers storing therein configuration header data of a physical PCI-to-PCI bridge device.